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FallenSigh 09fc1aeb44 Add CDMA endpoint path for matmul transfers

2026-07-01 20:15:55 +08:00

..

asm

Add CDMA endpoint path for matmul transfers

2026-07-01 20:15:55 +08:00

c_prg

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

coremark

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

dhrystone

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

dma

Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache

2026-06-24 02:04:40 +08:00

fft

Remove all debug and printf

2026-06-25 15:44:18 +08:00

fft_dma

Remove all debug and printf

2026-06-25 15:44:18 +08:00

fireye

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

hello_world

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

int_test

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

lenet

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

matmul_test

Rewrite matmul_test for CIC-IEC Stage 3 evaluation

2026-06-24 16:42:08 +08:00

mlkem_test

feat: add ML-KEM accelerator with AXI slave wrapper

2026-06-30 01:39:35 +08:00

pinball_game

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00