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FallenSigh 956cd67773 Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

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confreg.v

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

digitaltube_controller.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

int_ctrl.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

key_debounce.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00