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FallenSigh 3617ee7656 fix: change <= to = in array for loops for verilator BLKLOOPINIT

2026-06-30 02:15:14 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

fix: change <= to = in array for loops for verilator BLKLOOPINIT

2026-06-30 02:15:14 +08:00

sdk

fix: replace UNUSEDPARAM/UNUSEDSIGNAL with UNUSED for verilator lint

2026-06-30 02:10:07 +08:00

sim

Fix SRAM model: level-sensitive write for burst support

2026-06-25 15:40:28 +08:00

tools

add test data

2026-06-26 21:36:55 +08:00

.gitignore

chore: gitignore AI agent config directories (.claude .codex .opencode .agents)

2026-06-26 17:56:28 +08:00

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