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FallenSigh e35fa5884d Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache ...

The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).

2026-06-24 02:04:40 +08:00

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