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FallenSigh 16c0d7b639 Use __sync_synchronize() hardware barrier instead of asm compiler barrier

2026-06-24 23:22:38 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Revert pipeline: restore single-cycle compute

2026-06-24 22:23:53 +08:00

sdk

Use __sync_synchronize() hardware barrier instead of asm compiler barrier

2026-06-24 23:22:38 +08:00

sim

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

tools

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

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193 MiB

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