fallensigh/ciciec2026
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  • 9202327dd0 perf: batch UART FIFO writes — poll once per 16 bytes instead of per byte FallenSigh 2026-06-26 23:48:23 +08:00
  • 52e85aa6fb perf: drop stdint.h + picolibc — zero libc dependency FallenSigh 2026-06-26 22:34:26 +08:00
  • dd6053ab73 add test data FallenSigh 2026-06-26 21:36:55 +08:00
  • ac00518741 chore: untrack remaining agent config files (.claude/settings.json, .codex/config.toml) FallenSigh 2026-06-26 17:58:19 +08:00
  • c539182ecb chore: gitignore AI agent config directories (.claude .codex .opencode .agents) FallenSigh 2026-06-26 17:56:28 +08:00
  • eed9a83b3e chore: remove trellis infrastructure (agents, hooks, skills, tasks, spec) FallenSigh 2026-06-26 17:55:08 +08:00
  • ae89363227 perf(matmul): bypass printf — direct UART 16550 register writes FallenSigh 2026-06-26 17:51:13 +08:00
  • f55e15af32 perf(matmul): remove all DMA TAG writes (hardware ignores TAG register) FallenSigh 2026-06-26 17:49:39 +08:00
  • 07b670b4c9 perf(matmul): strip ALL timing — zero get_ns() calls, zero TIME_* output FallenSigh 2026-06-26 17:46:07 +08:00
  • 6aab84bf4b perf(matmul): remove diagnostic get_ns() calls from hot loop (v2 clean) FallenSigh 2026-06-26 17:44:13 +08:00
  • 20611157c3 tools: add extract_cbor_uart.py — extract UART output from CBOR trace files FallenSigh 2026-06-26 17:40:20 +08:00
  • 45731e05b7 perf(matmul): add pipeline timing diagnostics (v2.1) FallenSigh 2026-06-26 03:54:20 +08:00
  • 81c636fb56 perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle FallenSigh 2026-06-26 03:39:32 +08:00
  • a2b496ca8d Restore timing + switch to polling + disable CPU interrupts (IE=0) FallenSigh 2026-06-26 01:01:48 +08:00
  • 115466353d Remove timing instrumentation from user-sample.c FallenSigh 2026-06-26 00:34:44 +08:00
  • 8bc3d42ac6 Fix pipe_cnt range: issue 0-15 (16 rounds), acc 4-19, done at 20 FallenSigh 2026-06-25 22:26:07 +08:00
  • db9997b473 Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state FallenSigh 2026-06-25 22:09:20 +08:00
  • b3c0db19b9 Fix CRC32: use combinational stream_valid (was stuck-high causing repeated processing) FallenSigh 2026-06-25 20:53:56 +08:00
  • f8459f2478 Hardware CRC32 engine in matmul IP: 4-byte/cycle combinational, register at 0x010 FallenSigh 2026-06-25 20:40:08 +08:00
  • 76b5f30c6b Move MATMUL_DONE to last line FallenSigh 2026-06-25 20:11:45 +08:00
  • d9483a9d39 Add timing instrumentation for profiling (prologue/loop/epilogue/crc32) FallenSigh 2026-06-25 20:10:31 +08:00
  • 956cd67773 Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines FallenSigh 2026-06-25 20:03:53 +08:00
  • 57ba5d271d Remove all debug and printf FallenSigh 2026-06-25 15:44:18 +08:00
  • b331301584 Fix SRAM model: level-sensitive write for burst support FallenSigh 2026-06-25 15:40:28 +08:00
  • a24b5cff6e Add for writes to result region (addr 320-399) FallenSigh 2026-06-25 15:31:28 +08:00
  • a9958ee4fa BURST_LEN 47->63 (64 beats) FallenSigh 2026-06-25 04:08:18 +08:00
  • 4aba830a7d Add for B1_C read channel FallenSigh 2026-06-25 04:04:18 +08:00
  • 3cad98a811 Increase BURST_LEN to 47 (48 beats) to cover 192-byte C reads in one burst FallenSigh 2026-06-25 03:54:10 +08:00
  • b5ec0d2926 Fix escaped quotes in display FallenSigh 2026-06-25 03:45:18 +08:00
  • 9c6b321d59 Add in read channel to debug C register readback FallenSigh 2026-06-25 03:44:54 +08:00
  • 3fb93131e5 Simplify ACCUM debug: show expression value only FallenSigh 2026-06-25 03:43:46 +08:00
  • 86eab428a7 Use parenthesized pairwise addition to prevent synthesis truncation FallenSigh 2026-06-25 03:41:58 +08:00
  • fba86b01a8 Add in C_ACCUM to debug accumulation sum FallenSigh 2026-06-25 03:38:26 +08:00
  • 4e409f870c Register mult_p before accumulation to prevent synthesis glitches FallenSigh 2026-06-25 03:27:51 +08:00
  • 6c77fa2e38 Remove FFT controller, tie off slave 6 FallenSigh 2026-06-25 03:16:40 +08:00
  • d9d03b16c6 Fix: wait for ALL 4 multipliers to finish before accumulation FallenSigh 2026-06-25 03:07:49 +08:00
  • 54aa37adee Add debug output for C[0][0]/C[1][1]/C[2][3] of groups 0,1 FallenSigh 2026-06-25 03:03:10 +08:00
  • 2e5d793bbf Merge main (CRC32 fix) FallenSigh 2026-06-25 02:52:09 +08:00
  • 9ecda4aa7a Fix CRC32 table, remove debug output FallenSigh 2026-06-25 02:51:36 +08:00
  • ae8f2d1c2d Merge main (AXI ports fix) into no-fft FallenSigh 2026-06-25 02:35:04 +08:00
  • a2b3f72c76 Fix matmul AXI: add missing awlock/cache/prot ports, remove placeholder FallenSigh 2026-06-25 02:34:50 +08:00
  • 8e86d8693e Increase DMA FIFO depth to 128 (512 bytes) for burst support FallenSigh 2026-06-25 01:54:07 +08:00
  • 1e36883a7c Fix CRC32 table entry 187 FallenSigh 2026-06-25 01:26:53 +08:00
  • 3962058592 Fix CRC32 table entry 187 again (0x5CB30A04 -> 0x5CB36A04) FallenSigh 2026-06-25 01:24:04 +08:00
  • 31c2b53583 CRC32 on-the-fly from c_buf (bypass GCC volatile ExtRAM bug) FallenSigh 2026-06-25 01:19:57 +08:00
  • 292d3c7abf Remove placeholder comment FallenSigh 2026-06-25 00:53:42 +08:00
  • d3e1b5fda4 Add missing AXI4 ports: awlock/awcache/awprot/arlock/arcache/arprot FallenSigh 2026-06-25 00:53:28 +08:00
  • 828612164a Re-remove FFT module (leaked in from main merge) FallenSigh 2026-06-25 00:51:54 +08:00
  • acb158a392 Update matmul RTL, remove shift_add_mult.v FallenSigh 2026-06-25 00:47:43 +08:00
  • 5e467175ea Merge main (user mods) into no-fft FallenSigh 2026-06-25 00:43:53 +08:00
  • 641d055f18 User mods: matmul RTL + shift_add_mult + C program FallenSigh 2026-06-25 00:43:16 +08:00
  • 99c85f1a20 Rewrite burst logic with FFT-style state machine (W_IDLE/DATA/RESP, R_IDLE/DATA) FallenSigh 2026-06-25 00:22:30 +08:00
  • 27d818390f Remove assign s_axi_rlast (now procedural) FallenSigh 2026-06-25 00:18:09 +08:00
  • 494b8b9c5b Fix: s_axi_rlast must be output reg (assigned in always block) FallenSigh 2026-06-25 00:16:36 +08:00
  • f05c445ef3 Sync matmul IP (burst support) from no-fft FallenSigh 2026-06-25 00:12:02 +08:00
  • d5ad070ca0 Restore FFT module on main branch FallenSigh 2026-06-25 00:10:42 +08:00
  • 20d5a541ad Add burst write/read support to matmul AXI slave for DMA compatibility FallenSigh 2026-06-25 00:08:29 +08:00
  • 1660b283c4 Move DMA files to asm/, remove from common.mk FallenSigh 2026-06-24 23:52:30 +08:00
  • 5459538a04 Add dma.c to common.mk link list FallenSigh 2026-06-24 23:47:33 +08:00
  • 5dcee80b95 DMA-driven: A+B+C per group via DMA ch0/ch1, -O2 CRC32 from ExtRAM FallenSigh 2026-06-24 23:46:58 +08:00
  • a42568f635 Clean production code: -O2, read CRC32 from ExtRAM, remove all debug FallenSigh 2026-06-24 23:42:35 +08:00
  • c1fcb3c796 CRC32 on-the-fly from c_buf — bypass ExtRAM reads entirely FallenSigh 2026-06-24 23:38:06 +08:00
  • 07f8422d75 Fix CRC32 table entry 187: 0x5CB30A04 -> 0x5CB36A04 FallenSigh 2026-06-24 23:32:24 +08:00
  • 93361733f6 Definitive write test: write 0xDEADBEEF then read back FallenSigh 2026-06-24 23:29:00 +08:00
  • 16c0d7b639 Use __sync_synchronize() hardware barrier instead of asm compiler barrier FallenSigh 2026-06-24 23:22:38 +08:00
  • f0ebf1f5fa Output A0/B0/C0 for groups 0-3 and N-2,N-1 FallenSigh 2026-06-24 23:16:26 +08:00
  • 2c8f5d37f3 Add asm memory barrier before CRC32 to flush write buffer FallenSigh 2026-06-24 23:09:06 +08:00
  • afef1f1433 Add group 1 A/B/C debug output FallenSigh 2026-06-24 23:03:46 +08:00
  • 23bb112586 Print CRC32 loop counter to verify iteration count FallenSigh 2026-06-24 23:01:29 +08:00
  • 8ea98874a5 Inline CRC32 computation into main (bypass function call) FallenSigh 2026-06-24 22:52:08 +08:00
  • d27e147652 Fix escaped quotes FallenSigh 2026-06-24 22:50:14 +08:00
  • f6146bd467 Minimal debug: CRC32 self-test + group 0 rdback in one line FallenSigh 2026-06-24 22:49:06 +08:00
  • e39a655861 Add CRC32 self-test debug output FallenSigh 2026-06-24 22:42:46 +08:00
  • bbd3e3358b Fix extra brace in debug code FallenSigh 2026-06-24 22:38:18 +08:00
  • 3269e83d68 Debug: check ExtRAM write-back at start/mid/end of range FallenSigh 2026-06-24 22:36:29 +08:00
  • d39b5ecdae Revert pipeline: restore single-cycle compute FallenSigh 2026-06-24 22:23:53 +08:00
  • 4a67ca5c83 Add debug output for group 0 write-back and group 1 compute FallenSigh 2026-06-24 22:09:06 +08:00
  • 2edf058e97 Merge branch 'main' into no-fft FallenSigh 2026-06-24 21:41:50 +08:00
  • bbdc1fd7fe Fix linter: remove placeholder, fix DVI reg declarations FallenSigh 2026-06-24 21:40:59 +08:00
  • 5972facc0a Pipeline matmul multiplier: 2-stage to fix WNS FallenSigh 2026-06-24 21:40:34 +08:00
  • 5ee2833a2b Remove FFT module, tie off slave 6, fix linter issues FallenSigh 2026-06-24 20:54:28 +08:00
  • db2ad12dbb Add verilator pragma to suppress BLKLOOPINIT in DelayBuffer.v FallenSigh 2026-06-24 20:41:52 +08:00
  • aaefb04737 Sync asm/ (user-sample.c + Makefile) from test branch FallenSigh 2026-06-24 17:01:45 +08:00
  • f8edd878d4 Rewrite matmul_test for CIC-IEC Stage 3 evaluation FallenSigh 2026-06-24 16:42:08 +08:00
  • 4a5ecc8bdc Add debug output: print A[0..3], B[0..3], C[0..5] for group 0 FallenSigh 2026-06-24 16:35:43 +08:00
  • e35fa5884d Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache FallenSigh 2026-06-24 02:04:40 +08:00
  • b8a4fcc30b Fix matmul_base address: 0x1f500000 -> 0xbf500000 FallenSigh 2026-06-24 01:58:29 +08:00
  • ff6e572996 matmul_test: rewrite for ExtRAM flow, add IP error debug FallenSigh 2026-06-24 01:49:02 +08:00
  • fe8eff0aa0 Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists FallenSigh 2026-06-23 01:33:56 +08:00
  • fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC FallenSigh 2026-06-23 01:22:45 +08:00