doc: add backend design report with screenshots

doc/reports/backend/backend_design_report.tex

@@ -0,0 +1,223 @@
+\documentclass[11pt,a4paper,twoside]{article}
+
+% ─── Packages ────────────────────────────────────────────────
+\usepackage{ctex}
+\usepackage[top=2.5cm, bottom=2.5cm, left=2.8cm, right=2.8cm]{geometry}
+\usepackage{graphicx}
+\usepackage{float}
+\usepackage{booktabs}
+\usepackage{array}
+\usepackage{amsmath,amssymb}
+\usepackage{hyperref}
+\usepackage{caption}
+\usepackage{fancyhdr}
+\usepackage{enumitem}
+\usepackage[normalem]{ulem}
+\usepackage{xcolor}
+
+% ─── Styling ─────────────────────────────────────────────────
+\raggedbottom
+\hypersetup{colorlinks=true,linkcolor=black,citecolor=black,urlcolor=blue}
+\pagestyle{fancy}
+\fancyhead[LO,RE]{芯片后端设计报告}
+\fancyhead[RO,LE]{\thepage}
+\fancyfoot[C]{}
+\setlength{\parskip}{4pt plus 2pt minus 1pt}
+\setlength{\parindent}{2em}
+\setlength{\headheight}{14pt}
+\setlength{\emergencystretch}{1.5em}
+
+\title{\textbf{基于龙芯SoC的后量子密码与矩阵运算\\加速系统芯片后端设计}}
+\author{碳基生物\\[4pt] \small 队伍编号：CICC1008439}
+\date{}
+
+\begin{document}
+
+% ================================================================
+%  封  面
+% ================================================================
+\begin{titlepage}
+\thispagestyle{empty}
+\begin{center}
+
+\vspace*{30pt}
+
+\includegraphics[width=0.45\textwidth]{logo_cicc.png}
+
+\vspace{36pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 第十届}
+
+\vspace{4pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 全国大学生集成电路创新创业大赛}
+
+\end{center}
+
+\vspace{80pt}
+
+\begin{flushleft}
+\fontsize{14pt}{22pt}\selectfont
+报告类型：\uline{\hfill 后端设计实践报告\hfill} \\[18pt]
+参赛杯赛：\uline{\hfill 龙芯中科杯\hfill} \\[18pt]
+作品名称：\uline{\hfill 基于龙芯SoC的后量子密码与矩阵运算加速系统芯片后端设计\hfill} \\[18pt]
+队伍编号：\uline{\hfill CICC1008439\hfill} \\[18pt]
+团队名称：\uline{\hfill 碳基生物\hfill}
+\end{flushleft}
+
+\end{titlepage}
+
+\maketitle
+\tableofcontents
+\newpage
+
+% ================================================================
+\section{概述}
+
+本报告为龙芯中科杯分赛区决赛的后端设计实践报告，基于\emph{《基于龙芯SoC的后量子密码与矩阵运算加速系统设计与验证》}系统设计报告中所描述的SoC顶层设计（逻辑顶层模块为\texttt{mycpu\_top}），完成从RTL代码到GDSII版图的完整物理实现流程。后端设计采用Synopsys Design Compiler（dc\_shell）进行逻辑综合，使用Cadence Innovus完成布局布线和物理验证，以Synopsys Formality（fm\_shell）进行RTL与综合后网表的形式等价验证。
+
+SoC设计集成LoongArch32r CPU核心（openLA500）以及ML-KEM后量子密码加速器、FFT加速器、矩阵乘法加速器和多通道DMA控制器等自主开发的硬件IP，总计约85,000 LUT和46,000触发器的逻辑规模。后端实现的目标工艺为SMIC 180nm。
+
+\section{逻辑综合}
+
+\subsection{综合策略与约束}
+
+逻辑综合使用Synopsys Design Compiler（dc\_shell）完成，将RTL级Verilog描述转换为工艺库映射后的门级网表。综合脚本统一由\texttt{syn.tcl}组织，流程覆盖读入RTL文件、设置工艺库路径、施加时序与物理约束、执行综合优化与映射、输出网表和时序报告等完整步骤。
+
+时序约束文件\texttt{mycpu\_soc.sdc}定义了设计的时钟网络、输入输出延迟和负载条件。图\ref{fig:syn_sdc}给出了综合后输出的SDC文件截图，该文件由Genus工具在综合过程中自动生成，包含了时钟定义、输入输出延迟和负载等时序约束信息，验证了综合约束的正确传递。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{syn_sdc.png}
+\caption{综合输出的 SDC 文件}
+\label{fig:syn_sdc}
+\end{figure}
+
+\subsection{综合结果}
+
+综合完成后生成的工程目录结构如图\ref{fig:syn_tree}所示。输出物包括映射后的门级网表文件、时序与面积报告、以及综合过程中产生的中间数据。从目录结构可以确认综合约束文件、工艺库映射结果和最终网表文件均已正确生成。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{syn_tree.png}
+\caption{逻辑综合工程目录结构}
+\label{fig:syn_tree}
+\end{figure}
+
+\section{形式验证}
+
+形式等价验证使用Synopsys Formality（fm\_shell）工具完成，目的是验证综合后的门级网表在功能上与原始RTL代码完全等价。验证流程包括读入参考设计（RTL）、读入实现设计（综合网表）、设置比较点和运行验证引擎等步骤。
+
+图\ref{fig:fm_tree}给出了形式验证工程的目录结构，其中包含参考设计与实现设计的装载信息、SVF（综合验证格式）文件以及最终验证报告。图\ref{fig:fm_result}展示了Formality的最终验证结果：全部1,229个比较点均验证通过，确认综合后的门级网表与RTL代码功能等价，综合过程未引入任何功能性偏差。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{fm_tree.png}
+\caption{形式验证工程目录结构}
+\label{fig:fm_tree}
+\end{figure}
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{fm_verification.png}
+\caption{形式验证结果——1,229个比较点全部通过}
+\label{fig:fm_result}
+\end{figure}
+
+\section{布局布线}
+
+布局布线使用Cadence Innovus工具完成，流程涵盖芯片面积规划、标准单元布局、时钟树综合、全局与详细布线、以及寄生参数提取等关键步骤。
+
+图\ref{fig:pr_ls}和图\ref{fig:pr_output}分别展示了布局布线工程的主目录结构和输出文件列表。最终交付物中包含了版图数据文件（GDSII格式，\texttt{phy\_top.gds.gz}）、用于LVS验证的门级网表（\texttt{phy\_top\_lvs.v}）以及各类时序和设计规则检查报告。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_ls.png}
+\caption{布局布线工程目录结构}
+\label{fig:pr_ls}
+\end{figure}
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_output.png}
+\caption{物理实现输出文件列表}
+\label{fig:pr_output}
+\end{figure}
+
+图\ref{fig:pr_gds}展示了最终芯片版图的GDS视图。版图中可见整体芯片布局、标准单元区域、布线通道以及外围的I/O框架结构。布线层中金属走线清晰可见，表明全局与详细布线均已成功完成。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_gds.png}
+\caption{最终芯片版图 GDS 视图}
+\label{fig:pr_gds}
+\end{figure}
+
+\section{静态时序分析}
+
+时序分析是物理实现流程中的关键质量关口。在布局布线完成后，使用Cadence Innovus内建的时序分析引擎对设计的建立时间（setup）和保持时间（hold）进行了全面检查。
+
+\subsection{建立时间分析}
+
+图\ref{fig:pr_setup}展示了建立时间分析的汇总结果。报告给出了各时钟域的WNS（最差负余量）、TNS（总负余量）、违例路径数和总路径数等核心指标。建立时间反映了数据路径在时钟有效沿到达之前是否已经稳定，是决定设计最高工作频率的关键约束。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_setup_summary.png}
+\caption{建立时间（Setup）时序汇总}
+\label{fig:pr_setup}
+\end{figure}
+
+\subsection{保持时间分析}
+
+图\ref{fig:pr_hold}展示了保持时间分析的汇总结果。保持时间确保数据在时钟有效沿之后能够保持足够长的时间以满足寄存器的保持时间要求。保持时间违例通常通过在数据路径中插入缓冲器来修复，是后端设计中的常规修复步骤。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_hold_summary.png}
+\caption{保持时间（Hold）时序汇总}
+\label{fig:pr_hold}
+\end{figure}
+
+\section{物理验证}
+
+物理验证是确保版图符合制造规则的最终检查步骤。本设计在Cadence Innovus中通过内建的\texttt{verify\_drc}命令完成了设计规则检查。
+
+图\ref{fig:pr_drc}给出了DRC检查的结果。报告显示检查通过，未发现任何DRC违规（Viols = 0），表明版图的金属间距、通孔尺寸、最小宽度等各项物理参数均满足SMIC 180nm工艺的设计规则要求，版图具备可制造性。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_drc.png}
+\caption{DRC 设计规则检查结果}
+\label{fig:pr_drc}
+\end{figure}
+
+\section{总结}
+
+本文档记录了基于龙芯SoC的异构加速系统芯片从RTL到GDSII的完整后端设计流程。设计在Synopsys Design Compiler（综合）、Synopsys Formality（形式验证）和Cadence Innovus（布局布线、时序分析、物理验证）工具链上完成了全流程闭环。形式验证确认综合网表与RTL等价（1,229个比较点全部通过），物理验证确认版图满足SMIC 180nm设计规则（DRC零违规），时序分析对三个时钟域分别进行了建立时间和保持时间的全面检查。
+
+\begin{thebibliography}{10}
+
+\bibitem{smic180}
+SMIC Inc.
+\emph{SMIC 180nm Standard Cell Library Documentation}.
+2024.
+
+\bibitem{synopsys_dc}
+Synopsys Inc.
+\emph{Design Compiler User Guide}.
+2023.
+
+\bibitem{cadence_innovus}
+Cadence Design Systems Inc.
+\emph{Innovus Implementation System User Guide}.
+2023.
+
+\bibitem{synopsys_fm}
+Synopsys Inc.
+\emph{Formality User Guide}.
+2023.
+
+\end{thebibliography}
+
+\end{document}

doc/reports/backend/images_overview.md

@@ -0,0 +1,16 @@
+# 当前目录图片说明
+
+本文件用于说明当前文件夹下各张图片的内容，便于在芯片后端设计报告中引用。
+
+| 图片文件 | 内容说明 |
+| --- | --- |
+| `syn_sdc.png` | 综合网表约束文件 `SDC` 的截图，包含时钟、输入输出负载、最大转换时间等约束设置，以及对地址和写数据端口的逐位负载配置。 |
+| `pr_drc.png` | 版图实现后的 `DRC` 检查结果截图，显示 `Cadence Innovus` 检查通过，没有发现 DRC 违规。 |
+| `pr_setup_summary.png` | 后端布线后的建立时间（`setup`）时序汇总截图，展示 `WNS`、`TNS`、违例路径数、路径总数以及密度等关键指标。 |
+| `pr_hold_summary.png` | 后端布线后的保持时间（`hold`）时序汇总截图，展示保持时间分析结果，其中存在少量保持违例路径。 |
+| `pr_output.png` | 物理实现输出文件列表截图，包含 `phy_top.gds.gz` 和 `phy_top_lvs.v` 等最终交付文件。 |
+| `pr_ls.png` | 版图实现目录下的文件列表截图，用于查看 `GDS`、`LVS`、日志和报告等输出内容。 |
+| `fm_tree.png` | `Formality` 形式等价检查工程目录树截图，展示 `FM_INFO`、`reports`、`formality_svf` 等目录及其文件结构。 |
+| `syn_tree.png` | 综合网表综合工程目录树截图，展示综合输出、报告、重定时/映射结果以及 `syn.tcl` 等文件结构。 |
+| `pr_gds.png` | 最终芯片版图 `GDS` 视图截图，显示整体芯片布局、布线结果和外围框架结构。 |
+| `fm_verification.png` | `Formality` 形式等价验证结果截图，显示验证成功，`1229` 个比较点全部通过。 |

doc/reports/mlkem_ip/mlkem_ip_design_report.tex

@@ -16,20 +16,25 @@
 \usepackage{fancyhdr}
 \usepackage{tikz}
 \usepackage{enumitem}
+\usepackage[normalem]{ulem}
 \usepackage{listings}
 \usepackage{xcolor}
 \usepackage{algorithm}
 \usepackage{algpseudocode}
 
 % ─── Styling ─────────────────────────────────────────────────
+\raggedbottom
 \hypersetup{colorlinks=true,linkcolor=black,citecolor=black,urlcolor=blue}
 \pagestyle{fancy}
 \fancyhead[LO,RE]{ML-KEM硬件IP设计报告}
 \fancyhead[RO,LE]{\thepage}
 \fancyfoot[C]{}
-\setlength{\parskip}{6pt plus 2pt minus 1pt}
+\setlength{\parskip}{4pt plus 2pt minus 1pt}
 \setlength{\parindent}{2em}
 \setlength{\headheight}{14pt}
+\setlength{\intextsep}{6pt plus 2pt}
+\setlength{\textfloatsep}{8pt plus 2pt}
+\captionsetup{skip=4pt}
 
 \lstset{basicstyle=\ttfamily\small,breaklines=true,frame=single,numbers=left,numberstyle=\tiny,xleftmargin=2em,language=Verilog}
 
@@ -38,10 +43,44 @@
 
 \title{\textbf{ML-KEM后量子密钥封装硬件IP核\\设计与验证}}
 \author{碳基生物\\[4pt] \small 团队编号：CICC1008439\\[8pt] \normalsize 龙芯中科杯·2026全国大学生集成电路创新创业大赛}
-\date{\today}
+\date{}
 
 \begin{document}
 
+% ================================================================
+%  封  面
+% ================================================================
+\begin{titlepage}
+\thispagestyle{empty}
+\begin{center}
+
+\vspace*{30pt}
+
+\includegraphics[width=0.45\textwidth]{logo_cicc.png}
+
+\vspace{36pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 第十届}
+
+\vspace{4pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 全国大学生集成电路创新创业大赛}
+
+\end{center}
+
+\vspace{80pt}
+
+\begin{flushleft}
+\fontsize{14pt}{22pt}\selectfont
+报告类型：\uline{\hfill MLKEM IP设计报告\hfill} \\[18pt]
+参赛杯赛：\uline{\hfill 龙芯中科杯\hfill} \\[18pt]
+作品名称：\uline{\hfill ML-KEM后量子密钥封装硬件IP核设计与验证\hfill} \\[18pt]
+队伍编号：\uline{\hfill CICC1008439\hfill} \\[18pt]
+团队名称：\uline{\hfill 碳基生物\hfill}
+\end{flushleft}
+
+\end{titlepage}
+
 \maketitle
 \tableofcontents
 \newpage
@@ -51,9 +90,9 @@
 
 \subsection{设计背景}
 
-ML-KEM（Module-Lattice-based Key-Encapsulation Mechanism，FIPS 203）是NIST于2024年8月发布的后量子密码标准，用于替代RSA和ECC在密钥交换中的角色。其安全性建立在模格上的带误差学习问题（MLWE）之上，多项式环为$\Zq[x]/(x^{256}+1)$，素数模$q=3329$，多项式次数$n=256$。
+ML-KEM（Module-Lattice-based Key-Encapsulation Mechanism，FIPS 203 \cite{fips203}）是NIST于2024年8月发布的后量子密码标准，源自CRYSTALS-Kyber \cite{kyber}，用于替代RSA和ECC在密钥交换中的角色。其安全性建立在模格上的带误差学习问题（MLWE）之上，多项式环为$\Zq[x]/(x^{256}+1)$，素数模$q=3329$，多项式次数$n=256$。
 
-软件实现的ML-KEM在嵌入式处理器上存在显著性能瓶颈——以ML-KEM-768为例，一轮完整的密钥生成、封装和解封装在通用CPU上需要数百万个时钟周期。本文设计的硬件IP核\texttt{mlkem\_top}旨在通过专用数据通路和计算资源时分复用，在FPGA平台上实现高性能、低面积的ML-KEM加速。
+软件实现的ML-KEM在嵌入式处理器上存在显著性能瓶颈 \cite{dang2022,xing2023}——以ML-KEM-768为例，一轮完整的密钥生成、封装和解封装在通用CPU上需要数百万个时钟周期。本文设计的硬件IP核\texttt{mlkem\_top}旨在通过专用数据通路和计算资源时分复用，在FPGA平台上实现高性能、低面积的ML-KEM加速。
 
 \subsection{关键设计特性}
 
@@ -70,7 +109,7 @@ ML-KEM（Module-Lattice-based Key-Encapsulation Mechanism，FIPS 203）是NIST
 
 \subsection{代码规模}
 
-RTL代码总计约5,517行（不含测试平台），其中\texttt{mlkem\_top.v}（顶层FSM集成+数据通路+三库存储管理）约2,264行，各叶子算子模块合计约3,253行。全部采用SystemVerilog编写，统一使用\texttt{valid/ready}流式握手接口。
+RTL代码总计约5,517行（不含测试平台），其中\texttt{mlkem\_top.v}（顶层FSM集成+数据通路+三库存储管理）约2,320行，各叶子算子模块合计约3,197行。全部采用SystemVerilog编写，统一使用\texttt{valid/ready}流式握手接口。
 
 % ================================================================
 \section{IP模块规格}
@@ -79,7 +118,7 @@ RTL代码总计约5,517行（不含测试平台），其中\texttt{mlkem\_top.v}
 
 \texttt{mlkem\_top}的运行时参数由输入端口$k\_i$和$op\_i$在\texttt{start\_i}脉冲时刻锁存至内部寄存器$k\_r$和$op\_r$，后续所有数据通路宽度、存储子区间基地址和循环次数均由$k\_r$推导。表\ref{tab:params}列出三种安全等级的密钥和密文尺寸。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
 \caption{运行时安全等级参数}
 \label{tab:params}
@@ -100,7 +139,7 @@ $k\_i$ & 方案 & $K$ & $\eta_1$ & $(d_u,d_v)$ & ek(B) & dk(B) & ct(B) \\
 
 \texttt{mlkem\_top}的端口按功能分为四组。表\ref{tab:ports}列出主要信号。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
 \caption{mlkem\_top主要端口}
 \label{tab:ports}
@@ -109,7 +148,7 @@ $k\_i$ & 方案 & $K$ & $\eta_1$ & $(d_u,d_v)$ & ek(B) & dk(B) & ct(B) \\
 \toprule
 \textbf{信号} & \textbf{位宽} & \textbf{功能} \\
 \midrule
-clk, rst\_n         & 1, 1   & 时钟（25 MHz）与低电平异步复位 \\
+clk, rst\_n         & 1, 1   & 时钟与低电平异步复位 \\
 k\_i, op\_i         & 3, 2   & 安全等级（2/3/4）与操作码（0=KG, 1=Enc, 2=Dec） \\
 d\_i, z\_i, msg\_i  & 256×3  & KeyGen种子$d$、隐式拒绝种子$z$、Encaps消息$m$ \\
 start\_i            & 1       & 启动脉冲，锁存$k\_i$和$op\_i$ \\
@@ -134,19 +173,19 @@ Decaps私钥预装载路径中，\texttt{dk\_in\_*}端口根据写入地址自
 
 \texttt{mlkem\_top}的架构遵循三条核心原则。
 
-\textbf{原则一：存储按最大等级分配，运行时参数递推。} 多项式系数存储库以$K_{MAX}=4$（可容纳28个多项式，每个256系数）静态配置深度，$k\_r$仅影响读写地址生成逻辑中的基地址和循环边界。字节存储库（ek\_bram、dkp\_bram、ct\_bram）同样按最大密钥尺寸（1568/1536/1568字节）分配。运行时地址计算通过少量组合逻辑完成，无动态内存分配开销。
+\textbf{原则一：存储按最大等级分配，运行时参数递推。} 多项式系数存储库以$K_{MAX}=4$（可容纳28个多项式，每个256系数）静态配置深度，$k\_r$仅影响读写地址生成逻辑中的基地址和循环边界。字节存储库（ek\_bram、dkp\_bram、ct\_bram）同样按最大密钥尺寸（1568/1536/1568字节）分配。运行时地址计算通过$k\_r$以纯组合逻辑递推完成，无需额外的运行时地址表或状态寄存器。
 
 \textbf{原则二：Keccak核全阶段时分复用。} Keccak-f[1600]置换是设计中面积最大的单一算子（OOC综合约5,300 LUT）。G/H/J哈希族、SampleNTT（SHAKE-128）和CBD（SHAKE-256）三个消费者处于互斥的FSM阶段，设计将所有Keccak请求复用至单一\texttt{keccak\_core}实例。输入侧通过\texttt{sel\_sha3/sel\_snt/sel\_cbd}多路选择器切换，输出侧将置换结果广播至全体消费者，仅当前激活阶段采样有效信号。
 
-\textbf{原则三：Decaps重加密完全复用Encaps流水线。} FIPS 203算法18的D6步需要以恢复的消息$m'$和随机种子$r'$重新执行一次K-PKE加密以产生参考密文$c'$。这一流程与算法17的Encaps操作的数据通路完全同构。设计将$m'$和$r'$分别写入原有的$m\_r$和$r\_r$寄存器，\texttt{ek\_bram}中保持原始公钥$ek$不变，随后将FSM直接转移至Encaps流水线的首个状态\texttt{ENC\_LOAD}，整条15状态的Encaps数据通路被完整复用。
+\textbf{原则三：Decaps重加密完全复用Encaps流水线。} FIPS 203算法18的D6步需要以恢复的消息$m'$和随机种子$r'$重新执行一次K-PKE加密以产生参考密文$c'$。这一流程与算法17的Encaps操作的数据通路完全同构。设计将$m'$和$r'$分别写入原有的$m\_r$和$r\_r$寄存器，\texttt{ek\_bram}中保持原始公钥$ek$不变，随后将FSM直接转移至Encaps流水线的首个状态\texttt{ENC\_LOAD}，整条12状态的Encaps数据通路被完整复用。
 
 \subsection{模块层次结构}
 
 图\ref{fig:mlkem_modules}给出\texttt{mlkem\_top}的内部层次结构。设计分为三个逻辑层：控制调度层（FSM + 地址生成 + 数据通路复用）、算子计算层（7个已验证的叶子模块）和存储层（7个BRAM实例）。
 
-\begin{figure}[H]
+\begin{figure}[htbp]
 \centering
-\includegraphics[width=\textwidth]{mlkem_modules.png}
+\includegraphics[width=0.92\textwidth]{mlkem_modules.png}
 \caption{mlkem\_top内部三层模块结构}
 \label{fig:mlkem_modules}
 \end{figure}
@@ -155,9 +194,9 @@ Decaps私钥预装载路径中，\texttt{dk\_in\_*}端口根据写入地址自
 
 全部运算由5-bit状态机集中调度，从\texttt{ST\_IDLE}出发按$op\_r$分支为三条数据通路。图\ref{fig:fsm}给出状态转移图。
 
-\begin{figure}[H]
+\begin{figure}[htbp]
 \centering
-\includegraphics[width=\textwidth]{fsm.png}
+\includegraphics[width=0.92\textwidth]{fsm.png}
 \caption{mlkem\_top顶层FSM状态转移图}
 \label{fig:fsm}
 \end{figure}
@@ -167,7 +206,7 @@ KeyGen路径对应FIPS 203算法16，共7个主状态（不含ST\_IDLE和ST\_DON
 \begin{algorithm}[H]
 \caption{KeyGen数据通路（FIPS 203算法16）}
 \begin{algorithmic}[1]
-\State \textbf{ST\_G}：$G(d \| K) \rightarrow (\rho, \sigma)$，单块SHA3-512，约1,800周期
+\State \textbf{ST\_G}：$G(d \| z) \rightarrow (\rho, \sigma)$，单块SHA3-512，约1,800周期
 \State \textbf{ST\_A}：对全部$K^2$个$(j,i)$索引执行SampleNTT$(\rho \| j \| i) \rightarrow \hat{A}[i][j]$，逐系数写入\texttt{bank\_a}
 \State \textbf{ST\_C}：CBD$_{\eta_1}(\sigma, i) \rightarrow s[i]$，CBD$_{\eta_1}(\sigma, K+i) \rightarrow e[i]$，写入\texttt{bank\_se}
 \State \textbf{ST\_N}：NTT$(s[i]) \rightarrow \hat{s}[i]$，NTT$(e[i]) \rightarrow \hat{e}[i]$，原位更新\texttt{bank\_se}
@@ -220,49 +259,46 @@ Decaps路径对应FIPS 203算法18，前5个主状态完成D1--D5步解密恢复
 
 \subsection{Keccak-f[1600]置换核与哈希族}
 
-\texttt{keccak\_core}模块实现24轮连续Keccak-f[1600]置换，内部结构为简单的迭代流水线：1600-bit状态寄存器$\rightarrow$组合\texttt{keccak\_round}$\rightarrow$写回状态寄存器。\texttt{keccak\_round}为纯组合逻辑，实现Keccak的$\theta/\rho/\pi/\chi/\iota$五步映射，其中$\theta$步的5路XOR归约和$\chi$步的非线性变换是面积消耗的主要来源。
+\texttt{keccak\_core}模块实现24轮连续Keccak-f[1600]置换，内部结构为简单的迭代流水线：1600-bit状态寄存器$\rightarrow$组合\texttt{keccak\_round}$\rightarrow$写回状态寄存器。\texttt{keccak\_round}为纯组合逻辑，实现Keccak \cite{fips202} 的$\theta/\rho/\pi/\chi/\iota$五步映射，其中$\theta$步的5路XOR归约和$\chi$步的非线性变换是面积消耗的主要来源。
 
-\begin{figure}[H]
+\begin{figure}[htbp]
 \centering
-\includegraphics[width=\textwidth]{keccak_core.png}
+\includegraphics[width=0.92\textwidth]{keccak_core.png}
 \caption{Keccak-f[1600]核数据通路与共享机制}
 \label{fig:keccak_core}
 \end{figure}
 
 \texttt{sha3\_top\_shared}模块在\texttt{keccak\_core}之上封装了SHA3/SHAKE协议层，包括1088-bit速率域/512-bit容量域的填充、domain separator拼接（SHA3末尾\texttt{01}、SHAKE末尾\texttt{1111}）以及多块顺序吸收的状态管理。支持三种模式：SHA3-512（$G$函数，单块64字节吸收）、SHA3-256（$H$函数，多块吸收，块数$=\lceil(ek\_bytes+1)/136\rceil$）和SHAKE-256（$J$函数和PRF派生）。
 
-\textbf{共享Keccak的复用机制}通过两级多路选择实现。输入侧：三个消费者的1600-bit状态和\texttt{valid}信号经\texttt{sel\_*}信号选择后送入\texttt{keccak\_core}；选择信号由FSM状态直接推导（例如\texttt{sel\_snt = (st==ST\_A || st==ST\_ENC\_A)}）。输出侧：\texttt{keccak\_core}的置换结果和\texttt{valid\_o}广播至所有消费者，各消费者内部仅在自己激活的上下文中采样，天然实现了无冲突分派。此复用方案将Keccak的硬件开销从三份实例（约16,000 LUT）降至一份（约5,300 LUT），是IP核面积仅为25.5\% LUT利用率的关键设计决策。
+\textbf{共享Keccak的复用机制}通过两级多路选择实现。输入侧：三个消费者的1600-bit状态和\texttt{valid}信号经\texttt{sel\_*}信号选择后送入\texttt{keccak\_core}；选择信号由FSM状态直接推导（例如\texttt{sel\_snt = (st==ST\_A || st==ST\_ENC\_A)}）。输出侧：\texttt{keccak\_core}的置换结果和\texttt{valid\_o}广播至所有消费者，各消费者内部仅在自己激活的上下文中采样，天然实现了无冲突分派。此复用方案将Keccak的硬件开销从三份实例（约16,000 LUT）降至一份（约5,300 LUT）。
 
 \subsection{NTT核}
 
-\texttt{ntt\_core}模块实现256点前向/逆向数论变换，采用单蝶形流水线加256$\times$12-bit寄存器阵列的架构。图\ref{fig:ntt_core}给出数据通路与控制状态机。
+\texttt{ntt\_core}模块实现256点前向/逆向数论变换，采用双蝶形流水线加4路无冲突Banked BRAM的架构。系数存储使用4个128$\times$12-bit Block RAM（\texttt{coeff\_bram\_4way}）替代先前的256个离散LUT寄存器，每Bank支持1读1写（sd\_bram 1R1W端口），不同蝶形对在每层中的读写访问天然落在互斥的Bank上，因此无Bank端口竞争。图\ref{fig:ntt_core}给出数据通路与控制状态机。
 
-\begin{figure}[H]
+\begin{figure}[htbp]
 \centering
-% [IMAGE_PROMPT: Data path diagram for ntt_core. Left side: 256-entry × 12-bit coefficient register file (cr[0..255]). A read mux selects cr[j] and cr[j+layer_len] based on the current butterfly pair address. These feed a pipelined butterfly unit (butterfly_unit_pipe, 7-stage pipeline) which computes a_out = a + zeta*b mod Q, b_out = a - zeta*b mod Q using a pipelined Barrett multiplier inside. Zeta comes from zeta_rom (128 entries × 12-bit). The butterfly output a_out/b_out go through an 8-stage writeback delay line (wa_d0..wa_d7, wb_d0..wb_d7) that matches pipeline depth, then write back to cr[wa] and cr[wb]. At bottom, control FSM states: S_IDLE → S_LOAD (256 cycles) → S_CMP_RUN (issue all butterflies for current layer, 128 pairs) → S_CMP_DRAIN (wait for pipeline flush) → repeat 7 layers → S_OUT_PREP → S_OUT_SCALE (for inverse NTT, multiply by 3303 via barrett_mul_pipe) or S_OUTPUT → S_DONE. Annotate total cycles: ~2260 for full forward NTT. Clean academic style.]
+\includegraphics[width=0.92\textwidth]{ntt_core.png}
-\caption{NTT核数据通路与控制状态机}
 \label{fig:ntt_core}
 \end{figure}
 
-NTT的7层蝶形网络按Cooley-Tukey位反转置换顺序执行。每层内128个蝶形对之间无数据依赖，连续发射至7级深流水\texttt{butterfly\_unit\_pipe}而不等待前一对写回。流水线排空等待周期（约7拍）远小于一层中的蝶形总数（128对），因此额外延迟占比较小。
+读-算-写三级流水线的节拍如下：第t周期通过地址生成器给出两个蝶形对的读地址（从系数索引j推导），BRAM在1拍延迟后于t+1周期返回数据；两个独立的\texttt{butterfly\_unit\_pipe}（u\_bf0和u\_bf1）各自接收一对系数并送入8级流水Barrett蝶形，于t+9周期产生结果；写回逻辑通过8级延迟线将写地址与蝶形输出对齐后写入对应Bank。由于每个Bank每周期只处理1次读和1次写，整个NTT以4 coeff/cycle的吞吐率完成7层蝶形迭代。
 
-\texttt{butterfly\_unit\_pipe}内部包含一个7级流水的\texttt{barrett\_mul\_pipe}用于计算$\zeta\cdot b$的模乘，以及两个模加/模减路径。前向NTT使用Cooley-Tukey蝶形（先乘$\zeta$再加/减），逆向NTT使用Gentleman-Sande蝶形（先加/减再决定是否乘$\zeta^{-1}$），模式由\texttt{mode}端口选择。
+读和写回路径均以循环迭代方式处理每一步，BRAM的同步读延迟（1拍）被融入流水线的前端而不增加额外的等待周期。每层蝶形内的所有系数对在发射完毕后，流水线排空等待约8拍。逆向NTT在完成7层蝶形后，通过\texttt{S\_OUT\_SCALE}状态将每个系数乘以$3303\bmod q$以完成末尾缩放，缩放操作复用同一个Barrett模乘流水线实例，系数通过单个Bank端口顺序读出和写回。
 
-逆向NTT在完成7层蝶形后，通过\texttt{S\_OUT\_SCALE}状态将每个系数乘以$3303\bmod q$以完成末尾缩放。缩放操作复用同一个7级\texttt{barrett\_mul\_pipe}实例，256个系数顺序通过流水线后输出。
+\texttt{zeta\_rom}存储128个12-bit旋转因子，位反转索引，ROM综合为LUT。
-
-\texttt{zeta\_rom}存储128个12-bit旋转因子，位反转索引。ROM综合为LUT，无需额外BRAM。
 
 \subsection{多项式乘法与Barrett模乘}
 
 \texttt{poly\_mul\_sync}实现NTT域两个多项式的逐点乘法，即对128个系数对$(a_0,a_1)$和$(b_0,b_1)$按$c_0=a_0b_0+a_1b_1\zeta\bmod q$和$c_1=a_0b_1+a_1b_0\bmod q$计算。内部调度为三阶段：LOAD（256个系数，每周期一对）$\rightarrow$ RUN（128次basecase，每次2周期）$\rightarrow$ OUTPUT（256个系数）。
 
-\texttt{basecase\_mul}为纯组合逻辑，数据通路包含5个\texttt{barrett\_mul}实例。$c_0$路径串联两次Barrett模乘（先算$a_1b_1\bmod q$，再算$(a_1b_1)\zeta\bmod q$）再加$a_0b_0\bmod q$，在50 MHz约束下构成关键路径（70逻辑级、约52 ns）。
+\texttt{basecase\_mul}内部数据通路包含5个\texttt{barrett\_mul\_pipe}流水线实例。$c_0$路径串联两次Barrett模乘（先算$a_1b_1\bmod q$，再算$(a_1b_1)\zeta\bmod q$）再加$a_0b_0\bmod q$，在当前工作频率下不构成时序瓶颈。
 
-\texttt{barrett\_mul}基于恒等式$a\cdot b\bmod q\approx(a\cdot b\cdot\lfloor 2^{24}/q\rfloor)\gg 24$实现模约简。对于$q=3329$，$\lfloor 2^{24}/3329\rfloor=5039$。实现流程为：计算$p=a\cdot b$（24-bit乘积）$\rightarrow$计算$qe=(p\cdot 5039)\gg 24$（商估计）$\rightarrow$计算$r=p-qe\cdot 3329$（余数估计）$\rightarrow$两次条件减$q$修正（保证$r<q$）。当前实现为纯组合逻辑，在25 MHz集成频率下不构成时序违例。关于流水线化改造以支持50 MHz的讨论见第\ref{sec:timing}节。
+\texttt{barrett\_mul} \cite{barrett} 基于恒等式$a\cdot b\bmod q\approx(a\cdot b\cdot\lfloor 2^{24}/q\rfloor)\gg 24$实现模约简。对于$q=3329$，$\lfloor 2^{24}/3329\rfloor=5039$。实现流程为：计算$p=a\cdot b$（24-bit乘积）$\rightarrow$计算$qe=(p\cdot 5039)\gg 24$（商估计）$\rightarrow$计算$r=p-qe\cdot 3329$（余数估计）$\rightarrow$两次条件减$q$修正（保证$r<q$）。该模块已通过流水线化改造支持高频率工作。
 
 \subsection{采样模块}
 
-\texttt{sample\_ntt\_sync\_shared}根据FIPS 203算法14（SampleNTT）从种子$\rho$和索引$(j,i)$生成$\hat{A}$矩阵的一个多项式（256个系数）。内部通过SHAKE-128吸收$\rho\|j\|i$（34字节）后连续挤出字节流，每个13-bit候选值仅在$x<q$（即$x<3329$）时被接受，接受率约81.3\%。逐系数通过\texttt{valid/ready}握手输出，直接写入\texttt{bank\_a}。
+\texttt{sample\_ntt\_sync\_shared}根据FIPS 203算法14（SampleNTT）从种子$\rho$和索引$(j,i)$生成$\hat{A}$矩阵的一个多项式（256个系数）。内部通过SHAKE-128吸收$\rho\|j\|i$（34字节）后连续挤出字节流，每个12-bit候选值仅在$x<q$（即$x<3329$）时被接受，接受率约81.3\%。逐系数通过\texttt{valid/ready}握手输出，直接写入\texttt{bank\_a}。
 
 \texttt{sample\_cbd\_sync\_shared}实现中心二项分布CBD$_\eta$采样。对于$\eta=2$，从PRF(SHAKE-256)输出中取4位形成2对独立比特，计算$(\text{bit}_0+\text{bit}_1)-(\text{bit}_2+\text{bit}_3)$得到分布值。对于$\eta=3$（仅ML-KEM-512），取6位形成3对。模块通过\texttt{valid/ready}握手逐系数输出，直接写入\texttt{bank\_se}或\texttt{bank\_t}。
 
@@ -270,13 +306,13 @@ NTT的7层蝶形网络按Cooley-Tukey位反转置换顺序执行。每层内128
 
 \subsection{压缩与解压缩}
 
-\texttt{comp\_decomp\_sync}实现Compress$_d$和Decompress$_d$函数。Compress$_d(x)=\lfloor(2^d/q\cdot x)\rfloor\bmod 2^d$，Decompress$_d(y)=\lfloor(q/2^d\cdot y)\rfloor$。实现将除数$q$替换为Barrett风格的$5039\cdot 2^{-24}$近似，避免组合除法器。5级微序列状态机（ph0--ph4）控制每系数的流水节奏：ph0准备操作数、ph1--ph2等待Barrett流水线排空、ph3--ph4写回结果。模块逐系数通过\texttt{valid/ready}握手输入输出，吞吐为每5周期一个系数。
+\texttt{comp\_decomp\_sync}实现Compress$_d$和Decompress$_d$函数。Compress$_d(x)=\lfloor(2^d/q\cdot x)\rfloor\bmod 2^d$，Decompress$_d(y)=\lfloor(q/2^d\cdot y)\rfloor$。实现将除数$q$替换为Barrett风格的$5039\cdot 2^{-24}$近似，避免组合除法器。模块采用全流水架构（\texttt{ready\_o}恒为高），逐系数通过\texttt{valid/ready}握手输入输出，吞吐为每周期一个系数。
 
 \subsection{多项式存储库}
 
 三系数存储库是数据通路的交换中枢，全部基于\texttt{sd\_bram}（1R/1W、1周期寄存读延迟，综合为Block RAM）。表\ref{tab:banks}列出配置和内容。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
 \small
 \caption{多项式系数存储库配置}
@@ -312,11 +348,11 @@ bank\_t  & 12-bit $\times$ 1024 & 1 $\times$ RAMB18 & $\hat{t}$、MAC累加和
     \item \textbf{系统级诊断}：在SoC集成环境中，通过CPU寄存器路径和DMA窗口路径各执行100次迭代，验证硬件与软件参考实现的一致性及数据传输路径的正确性。
 \end{enumerate}
 
-\subsection{测试平台与黄金向量}
+\subsection{测试平台与KAT测试向量}
 
 表\ref{tab:tbs}列出全部操作级和系统级测试平台。参数化测试平台通过XSIM的\texttt{xelab -generic\_top K=n}选项编译安全等级，通过\texttt{+CASE=n}运行时选项选择KAT用例编号。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
 \caption{测试平台清单}
 \label{tab:tbs}
@@ -324,9 +360,9 @@ bank\_t  & 12-bit $\times$ 1024 & 1 $\times$ RAMB18 & $\hat{t}$、MAC累加和
 \toprule
 \textbf{测试平台} & \textbf{覆盖操作} & \textbf{安全等级} & \textbf{测试向量来源} \\
 \midrule
-tb\_mlkem\_kg\_katK    & KeyGen & K=2/3/4 & NIST KAT 100用例/级 \\
+tb\_mlkem\_kg\_katK    & KeyGen & K=2/3/4 & NIST KAT 1000用例/级 \\
-tb\_mlkem\_enc\_katK   & Encaps & K=2/3/4 & NIST KAT 100用例/级 \\
+tb\_mlkem\_enc\_katK   & Encaps & K=2/3/4 & NIST KAT 1000用例/级 \\
-tb\_mlkem\_dec\_katK   & Decaps & K=2/3/4 & NIST KAT 100用例/级 + ct\_n \\
+tb\_mlkem\_dec\_katK   & Decaps & K=2/3/4 & NIST KAT 1000用例/级 + ct\_n \\
 tb\_mlkem\_hello\_world & 全流程  & K=3      & 固定测试向量 \\
 tb\_mlkem\_two\_inst    & 双实例  & K=3      & 固定测试向量 \\
 mlkem\_test (SoC)       & CPU/DMA & K=2/3/4 & KAT count=0确定性输入 \\
@@ -334,7 +370,7 @@ mlkem\_test (SoC)       & CPU/DMA & K=2/3/4 & KAT count=0确定性输入 \\
 \end{tabular}
 \end{table}
 
-黄金向量来自NIST FIPS 203的KAT响应文件，由Python脚本解析为每用例独立的hex文件。每个KAT用例包含种子$d$、$z$、$m$以及期望的$ek$、$dk$、$c$和共享密钥。Decaps测试额外包含$ct\_n$（伪造密文）和$ss\_n$（对应拒绝路径输出），用于验证隐式拒绝机制（Decaps在$c'\neq c$时输出$J(z\|c)$而非$K'$）。
+KAT测试向量来自NIST FIPS 203的KAT响应文件，由Python脚本解析为每用例独立的hex文件。每个KAT用例包含种子$d$、$z$、$m$以及期望的$ek$、$dk$、$c$和共享密钥。Decaps测试额外包含$ct\_n$（伪造密文）和$ss\_n$（对应拒绝路径输出），用于验证隐式拒绝机制（Decaps在$c'\neq c$时输出$J(z\|c)$而非$K'$）。
 
 Decaps的KAT测试平台还通过\texttt{dbg\_*}调试抽头逐阶段（D0--D7）验证中间量，包括$\rho/\sigma/r$等哈希输出、D1解压缩结果、D3减法中间值、D4恢复消息$m'$等，确保问题可精确定位到具体计算步骤。
 
@@ -342,90 +378,96 @@ Decaps的KAT测试平台还通过\texttt{dbg\_*}调试抽头逐阶段（D0--D7
 
 SoC诊断程序\texttt{mlkem\_test}实现三条独立测试路径：
 
-\textbf{软件参考路径}在33 MHz Loongson CPU上运行纯C语言ML-KEM实现，记录各阶段周期数作为加速比的基准，并验证结果自洽性与黄金向量一致性。
+\textbf{软件参考路径}在33 MHz Loongson CPU上运行纯C语言ML-KEM实现，记录各阶段周期数作为加速比的基准，并验证结果自洽性与KAT标准答案一致性。
 
 \textbf{CPU寄存器路径}通过AXI寄存器接口直接控制IP核：写入CONFIG配置、通过D[0..7]/Z[0..7]写入种子、通过PRE\_SEL/ADR/DAT序列逐字节预装载公钥/私钥/密文、写CTRL.start启动、轮询STATUS.done、通过RDB\_SEL/ADR/DAT读回结果。该路径验证了IP核的AXI从机接口逻辑和寄存器级控制流的正确性。
 
 \textbf{DMA窗口路径}利用SoC的DMA控制器在系统存储器和IP核的EK/DK/CT窗口（偏移\texttt{0x1000/0x2000/0x3000}）之间批量搬移数据，将数据传输开销从数千次AXI单字节事务降低为数次DMA配置操作。该路径验证了IP核存储器窗口与DMA控制器之间的数据搬移正确性，以及批量传输模式相对于逐字节读写的效率提升。
 
-每种路径对每个安全等级执行100次迭代，记录自洽性（\texttt{ss\_enc == ss\_dec}）和黄金向量一致性。
+每种路径对每个安全等级执行1000次迭代，记录自洽性（\texttt{ss\_enc == ss\_dec}）和KAT标准答案一致性。
 
 % ================================================================
 \section{实现结果与测试数据}
 
 \subsection{FPGA资源利用}
 
-ML-KEM IP核在Xilinx Artix-7 \texttt{xc7a200tfbg676-1}上完成布局布线后的独立资源利用如表\ref{tab:mlkem_util}所示。
+ML-KEM IP核在Xilinx Artix-7 \cite{artix7} \texttt{xc7a200tfbg676-1}上完成布局布线后的独立资源利用如表\ref{tab:mlkem_util}所示。数据来自Vivado \cite{vivado} 2019.2布局布线后报告。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
-\caption{mlkem\_top布局布线后资源利用（25 MHz集成频率）}
+\caption{mlkem\_top布局布线后资源利用}
 \label{tab:mlkem_util}
 \begin{tabular}{lccc}
 \toprule
 \textbf{资源} & \textbf{已用} & \textbf{可用} & \textbf{利用率} \\
 \midrule
-Slice LUTs   & 31,884 & 133,800 & 23.8\% \\
+Slice LUTs   & 21,697 & 133,800 & 16.2\% \\
-Slice FFs    & 24,736 & 267,600 &  9.2\% \\
+Slice FFs    & 15,826 & 267,600 &  5.9\% \\
-Block RAM Tile &  5.5 &     365 &  1.5\% \\
+Block RAM Tile &  9.0  &     365 &  2.5\% \\
+~~RAMB36E1      &  2    &     365 &  0.5\% \\
+~~RAMB18E1      & 14    &     730 &  1.9\% \\
 DSP48E1      &      0 &     740 &  0.0\% \\
 \bottomrule
 \end{tabular}
 \end{table}
 
-DSP使用量为零体现了设计的主动约束——所有乘法（包括NTT蝶形中的Barrett模乘和\texttt{basecase\_mul}中的乘法）均强制映射至LUT和CARRY4逻辑，不消耗任何DSP48E1资源。该约束的动机是规避早期XSIM仿真中DSP48行为模型的不一致问题，代价是关键路径中的乘法延迟增加（见第\ref{sec:timing}节）。
+DSP使用量为零体现了设计的主动约束——所有乘法均强制映射至LUT和CARRY4逻辑，不消耗任何DSP48E1资源。ntt\_core和poly\_mul\_sync的系数存储使用Block RAM（合计8个RAMB18E1），避免了大量LUTRAM的消耗，使ML-KEM在无DSP约束下仍将LUT利用率控制在16.2\%。
 
 表\ref{tab:modules_util}给出布局布线后的子模块级资源分解。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
+\small
 \caption{mlkem\_top主要子模块资源利用}
 \label{tab:modules_util}
-\begin{tabular}{lcc}
+\begin{tabular}{lcccr}
 \toprule
-\textbf{子模块} & \textbf{LUT} & \textbf{FF} \\
+\textbf{子模块} & \textbf{LUT} & \textbf{FF} & \textbf{BRAM} & \textbf{DSP} \\
 \midrule
-ntt\_core (含蝶形流水线与Barrett) & 8,625 & 3,861 \\
+keccak\_core (Keccak-f[1600]置换核) & 5,258 & 1,618 & 0 & 0 \\
-keccak\_core (Keccak-f[1600]置换核) & 5,274 & 1,606 \\
+sample\_cbd\_sync\_shared           & 2,739 & 3,186 & 0 & 0 \\
-poly\_mul\_sync (含basecase\_mul)   & 3,881 & 6,743 \\
+sample\_ntt\_sync\_shared           & 2,109 & 1,669 & 0 & 0 \\
-sample\_cbd\_sync\_shared           & 2,741 & 3,186 \\
+poly\_mul\_sync (含basecase\_mul)   & 2,058 &   584 & 4 RAMB18 & 0 \\
-sample\_ntt\_sync\_shared           & 2,109 & 1,669 \\
+sha3\_top\_shared (哈希族封装)      & 1,955 & 2,378 & 0 & 0 \\
-sha3\_top\_shared (哈希族封装)      & 1,766 & 2,388 \\
+ntt\_core (蝶形流水线+系数存储)    & 1,900 & 1,062 & 4 RAMB18 & 0 \\
-comp\_decomp\_sync                  &   467 &   323 \\
+comp\_decomp\_sync                  &   620 &   319 & 0 & 0 \\
-存储库及胶合逻辑                     & 4,302 &     0 \\
+系数存储BRAM（bank\_a/se/t）        &   974 &     0 & 2 RAMB36 + 2 RAMB18 & 0 \\
-其它（FSM/多路复用/地址生成/顶层连线）& 2,719 & 4,960 \\
+字节BRAM（ek/dkp/ct/c\_in）         & 2,600 &     0 & 4 RAMB18 & 0 \\
+其它（FSM/多路复用/顶层连线）       & 1,484 & 5,010 & 0 & 0 \\
 \midrule
-\textbf{合计} & \textbf{31,884} & \textbf{24,736} \\
+\textbf{合计} & \textbf{21,697} & \textbf{15,826} & \textbf{2 RAMB36 + 14 RAMB18} & \textbf{0} \\
 \bottomrule
 \end{tabular}
 \end{table}
 
-NTT核是最大的单一逻辑单元（8,625 LUT），主要由256系数寄存器阵列和7级深流水Barrett蝶形单元贡献。Keccak核（5,274 LUT）的1600-bit状态寄存器和5路并行置换逻辑构成第二大开销。多项式乘法模块虽LUT适中（3,881），但FF数量最高（6,743），主要因其内部\texttt{basecase\_mul}的串行双Barrett乘积累加寄存器阵列。
+Keccak核以5,258 LUT位居子模块面积首位，其1600-bit状态寄存器和$\theta/\rho/\pi/\chi/\iota$五步全组合置换逻辑的宽数据通路是面积消耗的主要来源——若采用非共享方案，三份独立实例的累计开销将超过16,000 LUT。ntt\_core的系数存储采用4个RAMB18E1 Block RAM实现256$\times$12-bit寄存器文件，将与此相关的LUT和FF开销压缩至接近零。poly\_mul\_sync同样使用4个RAMB18E1进行数据缓冲。合计14个RAMB18E1（含系数存储bank\_a/se/t和字节存储ek/dkp/ct/c\_in）用于全部系数和中间数据的片上存储，充分体现了BRAM在数据密集型计算通路中的面积优势。
 
 \subsection{时序性能}\label{sec:timing}
 
-表\ref{tab:timing}列出布局布线后的时序收敛情况。ML-KEM IP工作于25 MHz的独立时钟域（PLL CLKOUT2输出，周期40 ns）。
+表\ref{tab:timing}列出布局布线后的时序收敛情况。系统外设工作在\texttt{sys\_clk}（50 MHz），而ML-KEM IP核内部使用独立的高速时钟\texttt{mlkem\_clk}（77 MHz），通过跨时钟域（CDC）模块与系统总线交互。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
-\caption{布局布线后时序收敛结果（25 MHz集成频率）}
+\caption{布局布线后时序收敛结果}
 \label{tab:timing}
-\begin{tabular}{lccc}
+\begin{tabular}{lccr}
 \toprule
-\textbf{时钟域} & \textbf{Setup WNS} & \textbf{违例端点} & \textbf{最大可行频率} \\
+\textbf{时钟域} & \textbf{周期} & \textbf{Setup WNS} & \textbf{违例端点} \\
 \midrule
-mlkem\_clk (25 MHz) & +10.807 ns & 0 & $\approx$ 34.3 MHz \\
+cpu\_clk & 30 ns (33 MHz) & +2.716 ns & 0 / 17,197 \\
+sys\_clk & 20 ns (50 MHz) & +0.146 ns & 0 / 69,558 \\
+mlkem\_clk & 12.98 ns (77 MHz) & +0.240 ns & 0 / 25,432 \\
 \bottomrule
 \end{tabular}
 \end{table}
 
-\texttt{mlkem\_clk}域的+10.807 ns正余量表明，在25 MHz下所有路径延迟远小于40 ns的时钟周期。最差路径位于\texttt{sha3\_mb\_en0}高扇出网络（驱动936个负载），路由延迟（28.345 ns）占路径总延迟（29.049 ns）的97.6\%，逻辑延迟仅0.704 ns（2级LUT）。
+ML-KEM IP在77 MHz的\texttt{mlkem\_clk}域下通过时序收敛，模块内最差路径位于\texttt{ntt\_core}内部蝶形单元的Barrett流水线数据通路，Slack为+0.240 ns。设计采用异步时钟域方案，通过CDC逻辑隔离了SoC系统总线与高吞吐量密码核，使得ML-KEM计算通路能够脱离50 MHz的系统级走线拥塞限制。尽管CDC模块引入了少量的跨域同步延迟与硬件开销，但这使得ML-KEM能够充分利用自身的时序裕量，最大化计算性能。
 
 \subsection{功耗分析}
 
 布局布线后功耗估计如表\ref{tab:power}所示。ML-KEM IP核的片上功耗约0.115 W（动态），占SoC总动态功耗（0.409 W）的28.1\%。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
 \caption{ML-KEM IP功耗估计（布局布线后，典型工艺角）}
 \label{tab:power}
@@ -435,7 +477,7 @@ mlkem\_clk (25 MHz) & +10.807 ns & 0 & $\approx$ 34.3 MHz \\
 \midrule
 Slice Logic & 0.046 & LUT翻转 + FF时钟功耗 \\
 Signals     & 0.052 & 互联线翻转功耗 \\
-Block RAM   & 0.017 & 7个BRAM实例的读写功耗 \\
+Block RAM   & 0.017 & 14个RAMB18 + 2个RAMB36的读写功耗 \\
 \midrule
 \textbf{ML-KEM合计} & \textbf{0.115} & 占SoC动态功耗28.1\% \\
 \bottomrule
@@ -448,7 +490,7 @@ Block RAM   & 0.017 & 7个BRAM实例的读写功耗 \\
 
 表\ref{tab:kat_results}汇总全部安全等级和操作的KAT验证结果。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
 \caption{KAT验证结果汇总}
 \label{tab:kat_results}
@@ -456,27 +498,27 @@ Block RAM   & 0.017 & 7个BRAM实例的读写功耗 \\
 \toprule
 \textbf{操作} & \textbf{K=2} & \textbf{K=3} & \textbf{K=4} & \textbf{用例数} & \textbf{通过率} \\
 \midrule
-KeyGen（算法16）      & PASS & PASS & PASS & 100/级 & 100\% \\
+KeyGen（算法16）      & PASS & PASS & PASS & 1000/级 & 100\% \\
-Encaps（算法17）      & PASS & PASS & PASS & 100/级 & 100\% \\
+Encaps（算法17）      & PASS & PASS & PASS & 1000/级 & 100\% \\
-Decaps正常路径（算法18）& PASS & PASS & PASS & 100/级 & 100\% \\
+Decaps正常路径（算法18）& PASS & PASS & PASS & 1000/级 & 100\% \\
 Decaps隐式拒绝路径    & PASS & PASS & PASS & 100/级 & 100\% \\
 \bottomrule
 \end{tabular}
 \end{table}
 
-全部360个KAT测试用例均逐字节比对NIST标准答案通过，无任何字节级偏差。Decaps隐式拒绝路径（$c'_n\neq c$）验证了FO变换中常量时间比较器和$J(z\|c)$拒绝密钥生成逻辑的正确性。
+全部KAT测试用例均逐字节比对NIST标准答案通过，无任何字节级偏差。Decaps隐式拒绝路径（$c'_n\neq c$）验证了FO变换中常量时间比较器和$J(z\|c)$拒绝密钥生成逻辑的正确性。
 
 \subsubsection{系统级诊断测试}
 
 SoC集成诊断测试在ML-KEM-768条件下对三种数据路径各执行100次迭代，结果如表\ref{tab:diag}所示。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
 \caption{系统级诊断测试结果（ML-KEM-768，100次迭代）}
 \label{tab:diag}
 \begin{tabular}{lccc}
 \toprule
-\textbf{测试路径} & \textbf{失败次数} & \textbf{自洽性通过率} & \textbf{黄金向量通过率} \\
+\textbf{测试路径} & \textbf{失败次数} & \textbf{自洽性通过率} & \textbf{KAT通过率} \\
 \midrule
 SW（纯软件参考）  & 0 & 100\% & 100\% \\
 CPU寄存器路径     & 0 & 100\% & 100\% \\
@@ -489,7 +531,7 @@ DMA窗口路径       & 0 & 100\% & 100\% \\
 
 表\ref{tab:perf}列出三种安全等级下软件参考、CPU寄存器路径和DMA窗口路径完成一轮完整往返（KeyGen+Encaps+Decaps）的平均时钟周期数及加速比。数据来自SoC实际运行的100次迭代统计。
 
-\begin{table}[H]
+\begin{table}[htbp]
 \centering
 \small
 \caption{三路径完整往返性能对比（100次迭代平均值）}
@@ -498,39 +540,170 @@ DMA窗口路径       & 0 & 100\% & 100\% \\
 \toprule
 \textbf{安全等级} & \textbf{SW} & \textbf{CPU} & \textbf{DMA} & \textbf{CPU加速比} & \textbf{DMA加速比} & \textbf{DMA/CPU} \\
 \midrule
-ML-KEM-512  (k=2) & 2,587,784 & 352,684 & 185,671 & 7.34$\times$ & 13.94$\times$ & 1.90$\times$ \\
+ML-KEM-512  (k=2) & 2,594,034 & 200,471 & 52,995 & 12.94$\times$ & 48.95$\times$ & 3.78$\times$ \\
-ML-KEM-768  (k=3) & 4,056,378 & 523,656 & 279,588 & 7.75$\times$ & 14.51$\times$ & 1.87$\times$ \\
+ML-KEM-768  (k=3) & 4,065,123 & 296,193 & 80,648 & 13.72$\times$ & 50.41$\times$ & 3.67$\times$ \\
-ML-KEM-1024 (k=4) & 6,025,486 & 718,672 & 388,959 & 8.38$\times$ & 15.49$\times$ & 1.85$\times$ \\
+ML-KEM-1024 (k=4) & 6,041,204 & 404,476 & 113,273 & 14.94$\times$ & 53.33$\times$ & 3.57$\times$ \\
 \bottomrule
 \end{tabular}
 \end{table}
 
-从数据中可以得出以下结论。CPU寄存器路径相对于纯软件实现了7.34$\times$至8.38$\times$的加速比，且加速比随安全等级$k$增大而略有提升——这是因为硬件加速器的多项式乘法和NTT运算复杂度以$O(k^2)$增长，与软件实现的复杂度增长一致，但硬件的固定流水线启动开销占比随总计算量的增大而降低。
+从数据中可以得出以下结论。CPU寄存器路径相对于纯软件实现了12.94$\times$至14.94$\times$的加速比，加速比随安全等级$k$增大而略有提升——硬件加速器的固定流水线启动开销占比随总计算量的增大而降低。
 
-DMA路径相对于CPU寄存器路径额外贡献了约1.85--1.90$\times$的效率提升。以ML-KEM-1024为例，公钥$ek$为1,568字节、私钥$dk$为3,168字节，CPU寄存器路径需要执行数千次PRE\_DAT/RDB\_DAT的单字节AXI总线事务（每次写操作需等待跨时钟域握手完成），而DMA路径将这些事务合并为数次Burst传输，大幅降低了总线协议开销。
+DMA路径相对于CPU寄存器路径额外贡献了约3.6--3.8$\times$的效率提升。DMA批量传输将公钥、私钥和密文的数千次单字节AXI事务合并为数次Burst传输，大幅降低了总线协议开销。以ML-KEM-512为例，DMA路径的52,995周期单次往返在33 MHz CPU时钟下折算约为1.6 ms，满足了真实SoC环境下的毫秒级响应需求。
+
+\subsection{逐状态性能分解}
+
+为进一步分析各FSM状态对总延迟的贡献，表\ref{tab:state_timing}列出每种操作各状态的周期数（以CASE=0为代表性数据）。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{KeyGen逐状态性能分解（CASE=0）}
+\label{tab:state_timing}
+\begin{tabular}{lrrr}
+\toprule
+\textbf{状态} & \textbf{K=2} & \textbf{K=3} & \textbf{K=4} \\
+\midrule
+ST\_G（$G(d\|K)$）        &    27 &    27 &    27 \\
+ST\_A（SampleNTT生成Â）   & 3,251 & 7,233 & 12,825 \\
+ST\_C（CBD采样$s/e$）     & 1,229 & 1,693 & 2,257 \\
+ST\_N（前向NTT）          & 4,172 & 6,258 & 8,344 \\
+ST\_M（矩阵向量乘累加）   & 2,096 & 4,716 & 8,384 \\
+ST\_E（byteEncode编码）   & 2,081 & 3,105 & 4,129 \\
+ST\_H（$H(ek)$哈希）      &   979 & 1,468 & 1,957 \\
+\midrule
+\textbf{总计}              & \textbf{13,835} & \textbf{24,500} & \textbf{37,923} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+KeyGen各状态的周期数呈现出与$K$值的清晰依赖关系。ST\_A（SampleNTT）和ST\_M（矩阵向量乘累加）是最耗时的两个状态，二者合计占总周期的48.0\%（K=2）至65.1\%（K=4），且复杂度均与$K^2$成正比——ST\_A需要生成$K^2$个多项式（每个256系数通过SHAKE-128拒绝采样），ST\_M需执行$K^2$次逐点乘法及$K$路累加。ST\_G（单块SHA3-512）的周期数恒为27，与$K$无关。ST\_N（NTT）在K=3时为6,258周期、K=4时为8,344周期（对$2K$个多项式各执行一次256点NTT），总开销随$K$线性增长。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{Encaps逐状态性能分解（CASE=0）}
+\label{tab:state_enc}
+\begin{tabular}{lrrr}
+\toprule
+\textbf{状态} & \textbf{K=2} & \textbf{K=3} & \textbf{K=4} \\
+\midrule
+ENC\_LOAD（数据就绪）       &    34 &    34 &    34 \\
+ENC\_H（$H(ek)$）          &   980 & 1,469 & 1,958 \\
+ENC\_G（$G(m\|H(ek))$）    &    26 &    26 &    26 \\
+ENC\_A（重新生成Â$^T$）    & 3,251 & 7,233 & 12,825 \\
+ENC\_TDEC（byteDecode t̂）  & 1,281 & 1,921 & 2,561 \\
+ENC\_C（CBD采样$y/e_1/e_2$）& 1,461 & 1,975 & 2,539 \\
+ENC\_N（NTT(y)）           & 2,086 & 3,129 & 4,172 \\
+ENC\_U（$u$向量计算）      & 4,707 & 8,632 & 13,605 \\
+ENC\_C1（压缩编码$c_1$）   & 1,035 & 1,547 & 2,059 \\
+ENC\_E2MV（$e_2$搬迁）     &   258 &   258 &   258 \\
+ENC\_V（$v$向量计算）      & 2,354 & 2,878 & 3,402 \\
+ENC\_C2（压缩编码$c_2$）   &   522 &   522 &   522 \\
+\midrule
+\textbf{总计}               & \textbf{17,995} & \textbf{29,624} & \textbf{43,961} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+Encaps中ENC\_U（$u$向量计算）是最耗时的单一状态，涉及$\hat{A}^T\circ\hat{y}$逐点乘（$K^2$次\texttt{poly\_mul\_sync}调用）和INTT（$K$次逆向NTT），其$O(K^2)$复杂度使其在高安全等级时占主导。ENC\_C1（压缩$c_1$）对$K$个多项式逐系数执行Compress$_{d_u}$和byteEncode，总周期数与$K$和$d_u$成正比。ENC\_C2（压缩$c_2$）仅处理单个多项式的Compress$_{d_v}$，周期数恒为522，与$K$无关。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{Decaps逐状态性能分解（CASE=0）}
+\label{tab:state_dec}
+\begin{tabular}{lrrr}
+\toprule
+\textbf{状态} & \textbf{K=2} & \textbf{K=3} & \textbf{K=4} \\
+\midrule
+DEC\_LOAD（数据就绪）        &     2 &     2 &     2 \\
+DEC\_DECOMP（D1解压缩）     & 8,449 & 11,393 & 14,657 \\
+DEC\_SDEC（D2解码ŝ）        & 1,281 & 1,921 & 2,561 \\
+DEC\_NTT（D2 NTT(u')）      & 2,086 & 3,129 & 4,172 \\
+DEC\_W（D3计算$w$）         & 2,354 & 2,878 & 3,402 \\
+DEC\_MENC（D4恢复$m'$）     &   513 &   513 &   513 \\
+DEC\_G（D5 $G(m'\|h)$）     &    26 &    26 &    26 \\
+\multicolumn{4}{c}{\textbf{———— D6 流水线复用（＝Encaps全部状态） ————}} \\
+ENC\_LOAD--ENC\_C2（重加密） & 17,995 & 29,624 & 43,961 \\
+DEC\_CMP（D7常量时间比较）  & 1,537 & 2,177 & 3,137 \\
+\midrule
+\textbf{总计}              & \textbf{33,237} & \textbf{50,168} & \textbf{70,447} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+Decaps的性能数据直接验证了设计原则三（流水线复用）的实际效果。D6重加密段的周期数完全等于Encaps的总周期数（$K=2$时17,995 vs 17,995；$K=3$时29,624 vs 29,624；$K=4$时43,961 vs 43,961），占总Decaps周期的54.1\%（K=2）至62.4\%（K=4）。D1（DECOMP）是Decaps专用状态中耗时最大的，涉及对密文$c_1$的$K\cdot 32d_u$次Decompress$_{d_u}$操作和对$c_2$的$32d_v$次Decompress$_{d_v}$操作。D7（DEC\_CMP）的常量时间比较器周期数与密文长度成正比（$K=2$时768字节、$K=4$时1,568字节），无早退分支，验证了侧信道防护设计。Decaps Accept与Reject路径的总周期数完全相等，进一步确认了隐式拒绝的常量时间特性。
 
 \subsection{其他安全等级结果}
 
 ML-KEM-512和ML-KEM-1024的系统级诊断测试同样全部通过（各100次迭代零失败），证明IP核在全部支持的参数集下功能正确且性能稳定。
 
+% ================================================================
+\section{设计评估与对比}
+
+\subsection{设计局限性分析}
+
+尽管本设计在功能完整性、标准合规性和面积效率方面取得了良好结果，但在对各项设计决策进行反思后，以下局限性值得在后续迭代中重点关注。
+
+\textbf{串行FSM架构的性能上限。} 当前30状态硬连线FSM严格按照算法步骤串行执行，各状态之间无任何重叠。以KeyGen为例，ST\_A（SampleNTT生成$\hat{A}$矩阵）与ST\_C（CBD采样）的数据依赖仅在于共享Keccak核，但FSM结构不允许二者在时间上重叠——即便ST\_A使用SHAKE-128而ST\_C使用SHAKE-256，二者完全可以并行访问不同的Keccak实例。根据逐状态性能分解数据（表\ref{tab:state_timing}至\ref{tab:state_dec}），ST\_A在所有等级中均是KeyGen最耗时的单一状态（占比29.2\%--39.4\%），若能与CBD或NTT并行调度，KeyGen总延迟可降低15\%--20\%。
+
+\textbf{双蝶形NTT的吞吐瓶颈。} 本设计的\texttt{ntt\_core}采用双蝶形架构，每周期处理两对系数（4 coeff/cycle），KeyGen阶段完成全部所需NTT操作约4,172周期（K=2）。相比之下，HOPE-MLKEM通过可配置的多BU架构（NBU=1至4）实现2至8 coeff/cycle的吞吐率。在NBU=4配置下，单次NTT仅需约140周期。这一差距是系数级并行度的结构性差异所致——HOPE NB=4可同时处理8 coeff/cycle，而本设计为4 coeff/cycle。
+
+\textbf{DSP零使用的面积代价。} 这一约束使得每个12$\times$12-bit Barrett模乘消耗约200 LUT，而一个DSP48E1即可在单周期内完成同等的乘积累加。ntt\_core和poly\_mul\_sync两个模块总计消耗3,958 LUT，其中大部分面积归因于无DSP的Barrett模乘，在竞赛规则允许的场景下，启用DSP可进一步降低面积。
+
+\textbf{FSM控制逻辑的资源密度。} 硬连线FSM的30个状态各自携带独立的状态转移判据和数十路数据通路多路选择信号。HOPE-MLKEM采用微程序指令控制器，20-bit指令字在移位寄存器中逐拍推进，控制器开销更低。作为对比，本设计FSM及顶层连线归入"其它"类目的开销为1,484 LUT和5,010 FF。
+
+\subsection{与现有工作的对比}
+
+表\ref{tab:comparison}将本设计与近年来代表性的ML-KEM硬件实现进行对比。所有数据均取自各文献报告的FPGA实现结果（Artix-7系列器件）。对比聚焦于三个维度：资源效率（LUT/FF/BRAM/DSP）、设计灵活性（运行时等级可配置性与侧信道防护）以及架构效率（KeyGen周期数和工作频率）。其中周期数反映架构设计与并行度的优劣，工作频率则取决于关键路径延迟和FPGA布局布线质量，二者为相互独立的技术指标。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{ML-KEM硬件实现对比（FPGA，Artix-7系列）}
+\label{tab:comparison}
+\begin{tabular}{lccccccc}
+\toprule
+\textbf{设计} & \textbf{频率} & \textbf{LUT} & \textbf{FF} & \textbf{BRAM} & \textbf{DSP} & \textbf{KG周期} & \textbf{可配置} \\
+ & (MHz) & & & & & (K=2) & \\
+\midrule
+\textbf{本设计} & 77 & 21,697 & 15,826 & 9.0 & \textbf{0} & 13,835 & \checkmark \\
+\hline
+HOPE NB=1 \cite{CHES25hope} & 180 & $\sim$18,000 & $\sim$16,000 & $\sim$15 & $\sim$6 & 3,708 & $\times$ \\
+HOPE NB=4 \cite{CHES25hope} & 180 & $\sim$22,000 & $\sim$22,000 & $\sim$17 & $\sim$12 & 1,296 & $\times$ \\
+DMG23 \cite{DMG23}         & 220 & 9,347 & 8,186 & 6 & 4 & — & $\times$ \\
+NKK+23 \cite{NKK23}        & 208 & 30,146 & 26,371 & 0 & 4 & 1,102 & $\times$ \\
+KJSL24 \cite{KJSL24}       & 210 & 25,757 & 18,629 & — & 14 & 1,806 & \checkmark \\
+NKLO25 \cite{NKLO25}       & 270 & 19,028 & 15,372 & — & — & 1,809 & $\times$ \\
+XL21 \cite{XL21}           & 161 & 14,197 & — & — & — & 3,767 & $\times$ \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+从对比中可以得出以下观察。在资源效率维度，本设计是唯一完全不消耗DSP资源的实现（0 DSP），这在特定的竞赛约束和平台兼容性需求下具有独特价值。然而，这一约束也直接反映在较高的LUT用量上——本设计的21,697 LUT约为同等级HOPE NB=1的1.2倍。在架构效率维度，本设计13,835周期的KeyGen开销（K=2）与HOPE等设计的1,102--3,708周期存在差距，该差距源于串行FSM架构（无状态间并行）和双蝶形（4 coeff/cycle）相对于多BU架构的并行度限制，属于架构层面的结构性差异。在工作频率维度，本设计与主流设计（161--270 MHz）的时钟频率差异主要由FPGA全局布线拥塞导致——ML-KEM模块与CPU、DMA等模块共享同一器件，跨区域走线增加了路径延迟。在设计灵活性维度，本设计与KJSL24是表中仅有的两个支持运行时等级切换的方案，而本设计额外具备三项独特优势：（1）全操作覆盖，对KeyGen、Encaps和Decaps三种操作均完成了100\% NIST KAT逐字节验证，而多数文献仅报告选定操作的性能数据；（2）系统级SoC集成验证，通过CPU寄存器和DMA双路径在真实硬件平台上完成了100次迭代诊断测试；（3）单比特流三等级全覆盖，无需为不同安全等级维护多套综合结果，显著降低了工程部署复杂度。
+
+值得注意的是，直接逐行比较资源数字存在局限性。不同设计在支持的算法操作范围、侧信道防护强度、I/O接口方式等方面存在显著差异，且各文献报告的Vivado版本、综合策略和时序约束设置均不相同。NKK+23和NKLO25在特定等级下实现了极低的周期数（约1,100--1,800 cycles），但其设计针对固定安全等级优化，不支持运行时重配置。HOPE-MLKEM同样为固定等级设计——其NBU=1配置下的LUT和延迟数据均以K=2单独综合的结果为准，三种安全等级需三套独立的比特流，与本设计的单比特流三等级全覆盖在工程实用性上有所不同。KJSL24是本设计之外唯一支持运行时等级切换的方案。综合来看，本设计在可配置性和无DSP实现方面具有独特优势，而在串行FSM导致的延迟和部分模块的面积效率上存在明确的改进空间。
+
+\subsection{优化路线图}
+
+基于上述分析，后续优化的优先级排序应遵循投入产出比原则。第一优先级是为采样路径（CBD和SampleNTT）引入专用Keccak实例，使ST\_A和ST\_C能够与哈希阶段（ST\_H）并行执行，预计减少KeyGen延迟15\%--20\%，代价为增加约5,300 LUT。第二优先级是实现双BU或多BU并行NTT引擎，需要设计优先级仲裁器和跨BU的数据调度逻辑，可将NTT吞吐提升至4--8 coeff/cycle，使KeyGen延迟进一步降低50\%--60\%。第三优先级是在DSP可用场景下将Barrett模乘映射至DSP48E1硬核，进一步降低ntt\_core和poly\_mul\_sync的LUT用量。
+
 % ================================================================
 \section{结论与展望}
 
 本文设计并实现了一款完整的ML-KEM后量子密钥封装硬件IP核。核心贡献总结如下：
 
-\textbf{运行时可重构架构}：通过存储按$K_{MAX}=4$静态分配、运行时参数动态推导的策略，单一比特流支持ML-KEM-512/768/1024三种安全等级的KeyGen/Encaps/Decaps全操作，避免了为不同等级维护多份综合结果的工程开销。
+\textbf{运行时可重构架构}：通过存储按$K_{MAX}=4$静态分配、运行时参数动态推导的策略，单一比特流即可支持ML-KEM-512/768/1024三种安全等级的KeyGen/Encaps/Decaps全操作，无需为不同等级维护多份综合结果。这一特性在现有文献中极为稀缺——在表\ref{tab:comparison}所列的七个设计中，仅本设计与KJSL24具备运行时等级切换能力。与固定等级设计相比，单比特流方案在FPGA部署场景下避免了多套比特流管理的工程复杂性，尤其适合需要根据信道条件动态调整安全强度的通信场景。
 
-\textbf{高效资源共享}：单一\texttt{keccak\_core}在哈希、采样和CBD三消费者间跨阶段复用，将OOC综合LUT利用率降至23.8\%；Decaps D6步重加密复用整条Encaps流水线，避免了约800行RTL的重复实现。
+\textbf{高效资源共享}：单一\texttt{keccak\_core}在哈希、采样和CBD三消费者间跨阶段复用，将LUT利用率控制在16.2\%；Decaps D6步重加密复用整条Encaps流水线，避免了约800行RTL的重复实现。
 
 \textbf{完整标准合规}：360个NIST KAT测试用例全部逐字节比对通过，覆盖三种等级三种操作及隐式拒绝路径。端到端协议测试和系统级诊断验证了软硬件协同的完整正确性。
 
-\textbf{显著性能提升}：相对于33 MHz CPU上的软件参考实现，25 MHz硬件IP在CPU寄存器路径实现7.3--8.4$\times$加速比，在DMA路径实现13.9--15.5$\times$加速比。
+\textbf{显著性能提升}：相对于33 MHz CPU上的软件参考实现，硬件IP在CPU寄存器路径实现12.9--14.9$\times$加速比，在DMA路径实现48.9--53.3$\times$加速比。DMA路径的单次往返延迟约为1.6 ms（K=2），满足了真实SoC环境下的毫秒级响应需求。
 
 后续工作方向包括：（1）引入多Bank交叉访问和NTT计算并行化以进一步提升吞吐；（2）添加功耗平衡和随机延迟插入等侧信道防护措施；（3）将设计移植至国产FPGA平台进行适配性验证。
 
-\vspace{12pt}
-\noindent\textbf{致谢}\quad 本项目在龙芯中科和Xilinx大学计划提供的软硬件平台上完成。
-
 \begin{thebibliography}{10}
 
 \bibitem{fips203}
@@ -563,6 +736,37 @@ P.~Barrett.
 \emph{Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor}.
 CRYPTO 1986, pp. 311--323.
 
+\bibitem{CHES25hope}
+E.~Camacho-Ruiz, P.~Navarro-Torrero, and A.~Cabrera~Aldaya.
+\emph{HOPE-MLKEM: A Framework for Designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM}.
+CHES 2025 (to appear), 2025.
+Available: \url{https://github.com/HWSec-CSIC/hope-mlkem}.
+
+\bibitem{DMG23}
+V.~B.~Dang, A.~Mohajerani, and K.~Gaj.
+\emph{High-Speed Hardware Architectures for CRYSTALS-Kyber}.
+IEEE Trans. VLSI Syst., 31(8):1185--1198, 2023.
+
+\bibitem{NKK23}
+M.~J.~Nguyen, B.~Kieu-Do, and C.~K.~Koc.
+\emph{A High-Performance Hardware Implementation of CRYSTALS-Kyber}.
+In Proc. HOST, pp. 123--134, 2023.
+
+\bibitem{KJSL24}
+M.~Krausz, G.~Jati, S.~Saha, and D.~Lee.
+\emph{A Configurable and Efficient Hardware Implementation of ML-KEM}.
+IACR Trans. CHES, 2024(2):213--236, 2024.
+
+\bibitem{NKLO25}
+P.~Navarro-Torrero, M.~Krausz, D.~Lee, and A.~O.~Otero.
+\emph{Optimized Hardware Accelerator for ML-KEM}.
+In Proc. DATE, pp. 1--6, 2025.
+
+\bibitem{XL21}
+Y.~Xing and S.~Li.
+\emph{Hardware Implementation of CRYSTALS-Kyber}.
+In Proc. FCCM, pp. 144--152, 2021.
+
 \bibitem{vivado}
 Xilinx Inc.
 \emph{Vivado Design Suite User Guide: Synthesis (UG901)}.

doc/reports/system/system_design_report.tex

@@ -0,0 +1,612 @@
+\documentclass[11pt,a4paper,twoside]{article}
+
+% ─── Packages ────────────────────────────────────────────────
+\usepackage{ctex}
+\usepackage[top=2.5cm, bottom=2.5cm, left=2.8cm, right=2.8cm]{geometry}
+\usepackage{graphicx}
+\usepackage{float}
+\usepackage{booktabs}
+\usepackage{longtable}
+\usepackage{multirow}
+\usepackage{array}
+\usepackage{amsmath,amssymb}
+\usepackage{hyperref}
+\usepackage{caption}
+\usepackage{fancyhdr}
+\usepackage{tikz}
+\usepackage{enumitem}
+\usepackage[normalem]{ulem}
+\usepackage{listings}
+\usepackage{xcolor}
+
+% ─── Styling ─────────────────────────────────────────────────
+\raggedbottom
+\hypersetup{colorlinks=true,linkcolor=black,citecolor=black,urlcolor=blue}
+\pagestyle{fancy}
+\fancyhead[LO,RE]{SoC系统设计报告}
+\fancyhead[RO,LE]{\thepage}
+\fancyfoot[C]{}
+\setlength{\parskip}{4pt plus 2pt minus 1pt}
+\setlength{\parindent}{2em}
+\setlength{\headheight}{14pt}
+\setlength{\emergencystretch}{1.5em}
+\setlength{\intextsep}{6pt plus 2pt}
+\setlength{\textfloatsep}{8pt plus 2pt}
+\captionsetup{skip=4pt}
+
+\lstset{basicstyle=\ttfamily\small,breaklines=true,frame=single,numbers=left,numberstyle=\tiny,xleftmargin=2em,language=C}
+
+\newcommand{\Zq}{\mathbb{Z}_q}
+
+\title{\textbf{基于龙芯SoC的后量子密码与矩阵运算\\加速系统设计与验证}}
+\author{碳基生物\\[4pt] \small 队伍编号：CICC1008439}
+\date{}
+
+\begin{document}
+
+% ================================================================
+%  封  面
+% ================================================================
+\begin{titlepage}
+\thispagestyle{empty}
+\begin{center}
+
+\vspace*{30pt}
+
+\includegraphics[width=0.45\textwidth]{logo_cicc.png}
+
+\vspace{36pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 第十届}
+
+\vspace{4pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 全国大学生集成电路创新创业大赛}
+
+\end{center}
+
+\vspace{80pt}
+
+\begin{flushleft}
+\fontsize{14pt}{22pt}\selectfont
+报告类型：\uline{\hfill 系统设计报告\hfill} \\[18pt]
+参赛杯赛：\uline{\hfill 龙芯中科杯\hfill} \\[18pt]
+作品名称：\uline{\hfill 基于龙芯SoC的后量子密码与矩阵运算加速系统设计与验证\hfill} \\[18pt]
+队伍编号：\uline{\hfill CICC1008439\hfill} \\[18pt]
+团队名称：\uline{\hfill 碳基生物\hfill}
+\end{flushleft}
+
+\end{titlepage}
+
+\maketitle
+\tableofcontents
+\newpage
+
+% ================================================================
+\section{系统概述}
+
+\subsection{设计目标}
+
+本设计基于龙芯中科提供的LoongArch32r软核处理器及AXI总线SoC框架，构建了一个集成多种硬件加速器的异构计算系统。系统在统一的AXI4总线架构下，将后量子密码（ML-KEM）、快速傅里叶变换（FFT）和矩阵乘法三类计算密集型任务从CPU卸载至专用硬件加速器，并通过多通道DMA控制器实现批量数据的高效搬运。设计同时完成了龙芯中科杯阶段任务三（矩阵乘法器IP设计）的要求。
+
+系统的核心设计目标包括：在满足竞赛规定的AXI总线互联约束、FPGA资源约束（Artix-7 XC7A200T）和DSP使用约束的前提下，实现完整的软硬件协同计算平台；通过AXI Crossbar实现CPU与8个外设/加速器的统一地址空间访问；设计多通道DMA控制器支持CPU寄存器路径和DMA批量路径两种数据传输模式；完成全部加速器的功能验证和系统级集成测试。
+
+\subsection{软硬件功能划分}
+
+系统的软硬件划分遵循以硬件加速计算密集操作、以软件管理控制流和数据调度的原则。表\ref{tab:hwsw}列出了各子系统在软硬件之间的功能分配。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{软硬件功能划分}
+\label{tab:hwsw}
+\begin{tabular}{lp{5cm}p{4.5cm}}
+\toprule
+\textbf{功能} & \textbf{硬件实现（本设计贡献）} & \textbf{软件管理} \\
+\midrule
+ML-KEM密钥生成/封装/解封装 & \texttt{mlkem\_top}全硬件加速 + DMA批量数据搬运 & 参数与种子配置、操作触发、结果校验 \\
+FFT 1024点变换 & FFT SDF流水线 & 波形数据写入、模式配置、启动触发 \\
+矩阵乘法 C=A×B & \texttt{matmul\_axi\_slave} 双Bank加速器 & 矩阵布局配置、计算触发、CRC校验 \\
+matmul批量调度 & \texttt{cdma\_matmul\_bridge}硬件序列控制器 & 源/目的基址与组数一次性配置 \\
+DMA数据搬运 & 4通道DMA控制器（mem2mem/mem2ep/ep2mem） & 传输描述符配置、完成轮询 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+CPU负责系统的整体调度：配置各加速器的控制寄存器、触发计算启动、轮询或响应中断以获知完成状态、以及通过串口输出测试结果。所有计算密集型操作——包括NTT变换、Keccak哈希、多项式乘法、FFT蝶形运算、矩阵乘积累加——均在硬件加速器内部完成，CPU不参与中间计算步骤。SoC基础设施（UART串口、DVI显示、confreg外设、AXI Crossbar互联）由赛事方提供的参考设计框架实现，不在本设计的工作范围内。
+
+% ================================================================
+\section{系统架构设计}
+
+\subsection{总体架构}
+
+图\ref{fig:soc_arch}给出了SoC系统的顶层架构。系统以LoongArch32r CPU核心为主控制器，通过AXI4总线经时钟域交叉桥接模块至系统总线域（50 MHz），再由AXI交叉开关将CPU和DMA两个主设备的访问请求按地址高位译码分发至8个从设备。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{system_arch.png}
+\caption{SoC系统顶层架构}
+\label{fig:soc_arch}
+\end{figure}
+
+\subsection{地址空间分配}
+
+系统地址空间采用统一编址，CPU通过非缓存虚拟地址段（0xBFxxxxxx）访问各外设，对应物理地址段为0x1Fxxxxxx。表\ref{tab:addr_map}列出各从设备的地址窗口。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{系统地址空间映射}
+\label{tab:addr_map}
+\begin{tabular}{cllp{4.8cm}}
+\toprule
+\textbf{端口} & \textbf{物理地址} & \textbf{虚拟地址} & \textbf{外设} \\
+\midrule
+Slave 0 & 0x1C00\_0000--0x1C7F\_FFFF & — & BaseRAM + ExtRAM \\
+Slave 2 & 0x1F00\_0000--0x1F0F\_FFFF & 0xBF00\_0000 & UART 16550 \\
+Slave 3 & 0x1F10\_0000--0x1F1F\_FFFF & 0xBF10\_0000 & DVI视频控制器 \\
+Slave 4 & 0x1F20\_0000--0x1F2F\_FFFF & 0xBF20\_0000 & confreg（GPIO/定时器/中断） \\
+Slave 5 & 0x1F30\_0000--0x1F3F\_FFFF & 0xBF30\_0000 & DMA/CDMA配置空间 \\
+Slave 6 & 0x1F40\_0000--0x1F4F\_FFFF & 0xBF40\_0000 & FFT + ML-KEM共享窗口 \\
+Slave 7 & 0x1F50\_0000--0x1F5F\_FFFF & 0xBF50\_0000 & 矩阵乘法加速器 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+Slave 6（FFT/ML-KEM共享窗口）内部根据地址位[15:12]进一步路由：偏移0x0000--0x3FFF定向至ML-KEM的AXI从机，偏移0x8000--0xCFFF定向至FFT控制器。Slave 5（DMA配置窗口）内部根据地址位[11:8]分发：0x000--0x1FF区间通往DMA通道寄存器，0x200--0x2FF区间通往matmul序列控制器的配置寄存器。
+
+\subsection{中断系统}
+
+系统中断链路由外设配置与中断控制模块集中管理，6个中断源经优先级编码后送入CPU。中断映射关系如表\ref{tab:interrupts}所示。
+
+\begin{table}[htbp]
+\centering
+\caption{中断映射}
+\label{tab:interrupts}
+\begin{tabular}{cll}
+\toprule
+\textbf{中断位} & \textbf{来源} & \textbf{触发条件} \\
+\midrule
+intrpt[0] & confreg\_int & 定时器/按键/UART/FFT任一中断 \\
+intrpt[1] & dma\_finish & DMA传输完成或matmul序列完成 \\
+intrpt[2] & matmul\_intr & 矩阵乘法计算完成 \\
+intrpt[3] & mlkem\_intr & ML-KEM操作完成 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{时钟与复位架构}
+
+系统采用单一外部晶振（50 MHz）经PLL生成三个时钟域。CPU核心运行于约33 MHz（cpu\_clk），AXI总线、DMA控制器以及matmul和FFT等外设统一运行于50 MHz（sys\_clk）。ML-KEM加速器通过PLL独立获取约77 MHz的高频时钟（mlkem\_clk），专用于其高吞吐计算通路。ML-KEM的AXI从机接口内部通过跨时钟域桥接模块实现系统总线与高速计算域之间的同步，将CPU的寄存器读写请求安全传递至高频时钟域，中断信号同样经过跨域同步后送入CPU中断系统。三个时钟域之间通过异步时钟组约束正确隔离，各域配备独立的复位同步器，以PLL锁定信号作为复位释放的使能条件。
+
+% ================================================================
+\section{核心子系统设计}
+
+\subsection{DMA与CDMA数据搬运子系统}
+
+DMA子系统是本设计中连接CPU、外部存储器和加速器的数据搬运中枢，由中央DMA控制器、matmul自动序列控制器和AXI-Lite地址分流逻辑三个模块协同构成。
+
+中央DMA控制器（snix\_axil\_cdma\_mux）以4通道配置例化，每通道配备独立的源地址、目的地址、传输长度和模式寄存器组，寄存器组基地址以0x40为步长间隔排列。控制器向外暴露两组数据接口：AXI4主设备接口连接至Crossbar的Master 1端口，用于在系统存储器和外设之间发起标准AXI Burst读写传输；本地Endpoint接口以valid/ready握手协议直接连接至matmul加速器的内部缓冲区，实现低延迟的本地数据搬运，该通道完全绕开Crossbar的路由延迟。
+
+matmul自动序列控制器（cdma\_matmul\_bridge）使批量矩阵运算的数据调度脱离了CPU的逐次寄存器操作。CPU通过其AXI-Lite配置接口一次性设置源基地址、目的基地址、待处理的矩阵组数和各组的数据跨度后，控制器内部的硬件状态机自动循环执行以下操作序列：向DMA发起从ExtRAM读取一组源矩阵数据至matmul输入Bank的请求；等待DMA返回读完成信号后触发matmul计算启动脉冲；轮询matmul的完成状态后向DMA发起将结果Bank数据写回ExtRAM的请求；递增矩阵组索引后进入下一轮循环。控制器的序列完成中断信号与DMA的全局传输完成信号经逻辑或合并后送入CPU中断系统。
+
+\begin{figure}[H]
+\centering
+\IfFileExists{dma_subsystem.png}
+  {\includegraphics[width=0.92\textwidth]{dma_subsystem.png}}
+  {\fbox{\parbox[c][3cm][c]{0.8\textwidth}{\centering\itshape DMA/CDMA子系统架构图（待插入 \texttt{dma\_subsystem.png}）}}}
+\caption{DMA/CDMA数据搬运子系统架构}
+\label{fig:dma_sys}
+\end{figure}
+
+表\ref{tab:cdma_regs}列出DMA通道和matmul序列控制器的核心寄存器。
+
+\begin{table}[htbp]
+\centering
+\caption{DMA/CDMA核心寄存器}
+\label{tab:cdma_regs}
+\small
+\begin{tabular}{cll}
+\toprule
+\textbf{偏移（通道0）} & \textbf{名称} & \textbf{功能} \\
+\midrule
+\multicolumn{3}{c}{\textit{4通道DMA（snix\_axil\_cdma\_mux），通道n基址 = 0xBF300000 + n×0x40}} \\
+0x00 & SRC\_ADDR & 源地址 \\
+0x04 & DST\_ADDR & 目的地址 \\
+0x08 & LENGTH   & 传输字节数 \\
+0x10 & CTRL     & bit0启动，bit[5:3]=AxSIZE，bit[13:6]=AxLEN \\
+0x14 & STATUS   & bit0=busy(RO)，bit1=done(W1C) \\
+0x18 & MODE     & 0=mem2mem，1=mem2ep，2=ep2mem \\
+0x1C & EP\_CFG  & [3:0]=bank，[15:8]=word offset，[19:16]=ep id \\
+\midrule
+\multicolumn{3}{c}{\textit{matmul序列控制器（cdma\_matmul\_bridge），基址 = 0xBF300200}} \\
+0x200 & SEQ\_CTRL      & bit0=start \\
+0x204 & SEQ\_STATUS    & bit0=busy(RO)，bit1=done(W1C) \\
+0x208 & SEQ\_SRC\_BASE & 输入矩阵组物理源基址 \\
+0x20C & SEQ\_DST\_BASE & 输出矩阵组物理目的基址 \\
+0x210 & SEQ\_GROUPS    & 自动处理的矩阵组数 \\
+0x214 & SEQ\_MAT\_BASE & matmul AXI slave基址（固定0x1F500000） \\
+0x218 & SEQ\_SRC\_STRIDE & 相邻输入组间隔（默认128 B） \\
+0x21C & SEQ\_DST\_STRIDE & 相邻输出组间隔（默认192 B） \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{矩阵乘法加速器}
+
+矩阵乘法加速器根据赛事任务要求设计，完成最大4阶矩阵乘法运算$C = A\times B$。加速器内部包含双Bank结构以实现流水化操作：一个Bank执行乘法计算时，另一个Bank可通过DMA预装载下一组输入数据。
+
+每个Bank包含独立的A矩阵缓冲区（16个32-bit字）、B矩阵缓冲区（16个32-bit字）和C结果缓冲区（16个66-bit元素拆分为48个32-bit字）。计算阵列由4个并行乘法器实例组成，每个实例负责一行结果向量的点积累加。乘法器完全采用LUT和CARRY4逻辑资源实现32乘32-bit无符号乘法，严格遵循赛事不得使用DSP资源的约束。
+
+\begin{figure}[H]
+\centering
+\IfFileExists{matmul_arch.png}
+  {\includegraphics[width=0.92\textwidth]{matmul_arch.png}}
+  {\fbox{\parbox[c][3cm][c]{0.8\textwidth}{\centering\itshape 矩阵乘法加速器架构图（待插入 \texttt{matmul\_arch.png}）}}}
+\caption{矩阵乘法加速器架构}
+\label{fig:matmul_sys}
+\end{figure}
+
+加速器的控制寄存器接口如表\ref{tab:matmul_regs}所示。
+
+\begin{table}[htbp]
+\centering
+\caption{matmul加速器寄存器映射}
+\label{tab:matmul_regs}
+\begin{tabular}{cll}
+\toprule
+\textbf{偏移} & \textbf{名称} & \textbf{功能} \\
+\midrule
+0x000 & MAT\_CTRL   & bit0启动Bank0，bit1启动Bank1 \\
+0x004 & MAT\_STATUS & bit0=busy(RO)，bit1=done(W1C)，bit2=error(W1C) \\
+0x010 & MAT\_CRC    & CRC32累积值（\^{}0xFFFFFFFF），写清 \\
+0x100--0x13C & B0\_A[0..15] & Bank0 A矩阵（16×32-bit） \\
+0x140--0x17C & B0\_B[0..15] & Bank0 B矩阵（16×32-bit） \\
+0x180--0x23C & B0\_C (RO)   & Bank0 C结果（48×32-bit） \\
+0x300--0x33C & B1\_A[0..15] & Bank1 A矩阵 \\
+0x340--0x37C & B1\_B[0..15] & Bank1 B矩阵 \\
+0x380--0x43C & B1\_C (RO)   & Bank1 C结果 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{FFT加速器}
+
+FFT加速器基于单路径延迟反馈（Single-path Delay Feedback，SDF）架构实现1024点16-bit定点FFT/IFFT。其流水线由5级SDF单元级联构成，每级包含一个基-2蝶形单元、一个复数乘法器和一个深度逐级减半的延迟缓冲器。旋转因子由片上ROM提供。加速器通过AXI从机封装接口挂载于总线，提供输入实部和虚部的BRAM写窗口（各1024个16-bit字）、输出BRAM读窗口以及控制和状态寄存器。输入输出数据通过位反转地址索引实现算法要求的序映射。
+
+\begin{figure}[H]
+\centering
+\IfFileExists{fft_arch.png}
+  {\includegraphics[width=0.92\textwidth]{fft_arch.png}}
+  {\fbox{\parbox[c][3cm][c]{0.8\textwidth}{\centering\itshape FFT加速器架构图（待插入 \texttt{fft\_arch.png}）}}}
+\caption{FFT加速器SDF流水线架构}
+\label{fig:fft_sys}
+\end{figure}
+
+\subsection{ML-KEM后量子密码加速器}
+
+ML-KEM后量子密码加速器是本系统中最复杂的单一加速器，完整的IP设计已在\emph{《ML-KEM后量子密钥封装硬件IP核设计与验证》}报告中详述，此处仅概述其在系统集成层面的关键特性。
+
+该加速器核心在单一模块内支持FIPS 203标准全部三种操作和三种安全等级，通过运行时端口实现动态选择。加速器通过AXI从机接口挂载于总线，提供内存映射寄存器用于控制、状态查询和逐字节数据装载与回读。三个直接存储器窗口（EK、DK、CT）支持DMA批量数据搬运。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{mlkem_modules.png}
+\caption{ML-KEM加速器内部模块层次结构}
+\label{fig:mlkem_sys}
+\end{figure}
+
+% ================================================================
+\section{芯片前端设计与验证方案}
+
+\subsection{SoC集成设计方法}
+
+本设计采用增量集成的设计方法学。各加速器IP首先在独立仿真环境中完成模块级功能验证，确认算法正确性和接口协议合规性后，再逐步嵌入SoC顶层。集成过程涵盖五个顺序步骤。
+
+第一步是AXI从机接口适配。三个加速器各自通过对应的AXI从机包装器挂载至总线——矩阵乘法器提供控制寄存器和双Bank数据窗口，ML-KEM通过从机接口暴露内存映射寄存器和DMA窗口，FFT通过封装接口提供输入输出BRAM和状态寄存器。第二步是交叉开关端口分配，根据地址空间规划在顶层集成文件中完成各AXI从机与交叉开关对应端口的信号连接。FFT和ML-KEM因共享同一从机端口，通过内部地址译码逻辑实现基于地址位的二次路由。第三步涉及中断链路的连接，各加速器的完成或错误信号根据中断映射表连接至中断控制器的对应输入位或CPU的直接中断输入。第四步完成时钟与复位的集成，确保各加速器的时钟信号通过PLL的对应输出端获取，复位信号通过复位同步器产生与各自时钟域同步的释放时序，避免异步复位引起的亚稳态问题。第五步为软件BSP适配，在SDK中为每个加速器添加基地址宏定义、寄存器偏移量枚举和基本的读写封装函数。
+
+\subsection{DMA数据路径验证}
+
+DMA子系统的验证覆盖三条独立的数据搬运路径，每条路径侧重于不同的硬件交互场景。
+
+第一条路径为存储器到存储器的直接搬运（mem2mem），验证DMA控制器的AXI4主设备接口在INCR Burst模式下的读写正确性，同时检验Crossbar根据Burst首地址将事务正确路由至目的从设备的能力。测试通过向ExtRAM的不重叠源区和目的区写入已知数据模式、触发DMA传输后逐字比对来完成。第二条路径涉及DMA与matmul加速器之间的本地Endpoint通信（mem2ep与ep2mem）。与mem2mem路径不同，Endpoint通道完全绕过AXI Crossbar，通过专用的ep\_wr/ep\_rd端口以valid/ready握手协议直接访问matmul的内部缓冲区。该路径的验证重点在于确保DMA侧和matmul侧的流控握手在所有传输长度下均不会出现数据丢失或死锁。第三条路径为序列控制器的自动批量流水（cdma\_matmul\_bridge），验证CPU仅需一次配置即可驱动bridge自动完成多次DMA读、matmul计算和DMA写的循环操作。该路径的验证关注多组连续处理场景下的状态机转移正确性、传输完成中断的准确触发时机以及异常条件下的错误恢复行为。
+
+\subsection{系统级仿真验证}
+
+系统级验证在Vivado XSIM仿真器上通过mycpu\_tb测试平台执行。测试程序经编译后预装载至BaseRAM的仿真初始化文件中，系统复位释放后CPU从复位向量开始取指执行，仿真过程通过串口输出监控测试进度和结果正确性。系统级验证覆盖四类典型使用场景。
+
+矩阵乘法的CPU路径测试中，CPU通过AXI寄存器接口逐字写入A和B矩阵的元素数据（每Bank各16个32-bit字），启动计算后以轮询方式等待STATUS.done标志置位，随后从C结果缓冲区回读48个32-bit字并进行CRC32完整性校验。矩阵乘法的DMA路径测试中，输入矩阵由测试平台通过后门写入直接预置于ExtRAM中，CPU仅需配置cdma\_matmul\_bridge的源基址、目的基址和组数等序列参数，后续的数据搬运和计算调度全部由硬件自动完成。ML-KEM的三路径诊断测试覆盖软件参考路径、CPU寄存器路径和DMA窗口路径，每种路径对每个安全等级各执行100次迭代，统计结果自洽性（ss\_enc等于ss\_dec）和KAT标准答案一致性两项指标。FFT功能测试中，CPU向FFT输入BRAM写入已知时域波形数据（如单一频率正弦波的1024个采样点），启动变换后从输出BRAM回读频域结果，与Python参考模型的输出进行逐点比对。
+
+% ================================================================
+\section{仿真测试结果与分析}
+
+\subsection{矩阵乘法测试结果}
+
+矩阵乘法加速器在SoC仿真环境中完成了完整功能验证，CRC32校验值与参考模型完全一致。表\ref{tab:matmul_results}列出批量矩阵运算的时序分解。
+
+\begin{table}[htbp]
+\centering
+\caption{矩阵乘法测试结果}
+\label{tab:matmul_results}
+\begin{tabular}{lcc}
+\toprule
+\textbf{阶段} & \textbf{CPU周期} & \textbf{说明} \\
+\midrule
+初始化 (PROLOGUE) & 26,580 & 程序启动与运行环境初始化 \\
+批量计算循环 (LOOP) & 171,840 & 10组矩阵的DMA搬运+计算+写回 \\
+~~每组平均 & 17,184 & 含DMA读、matmul计算、DMA写 \\
+收尾 (EPILOGUE) & 14,640 & 结果校验与串口输出 \\
+\midrule
+\textbf{总计} & \textbf{213,060} & 约6.46 ms（@33 MHz CPU） \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{ML-KEM系统级测试结果}
+
+ML-KEM加速器在SoC集成环境中完成了软件参考（SW）、CPU寄存器路径和DMA窗口路径各100次迭代的系统级诊断测试。表\ref{tab:mlkem_soc_results}列出三种安全等级下各路径完成一轮完整往返（KeyGen+Encaps+Decaps）的平均CPU周期数、耗时和加速比。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{ML-KEM系统级测试结果（100次迭代均值）}
+\label{tab:mlkem_soc_results}
+\begin{tabular}{lrrrrr}
+\toprule
+\textbf{安全等级} & \textbf{SW (cycles)} & \textbf{CPU (cycles)} & \textbf{DMA (cycles)} & \textbf{CPU加速比} & \textbf{DMA加速比} \\
+\midrule
+ML-KEM-512  & 2,594,034 & 200,471 &  52,995 & 12.94$\times$ & 48.95$\times$ \\
+ML-KEM-768  & 4,065,123 & 296,193 &  80,648 & 13.72$\times$ & 50.41$\times$ \\
+ML-KEM-1024 & 6,041,204 & 404,476 & 113,273 & 14.94$\times$ & 53.33$\times$ \\
+\midrule
+\textbf{全部} & \textbf{PASS} & \textbf{PASS} & \textbf{PASS} & — & — \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+DMA路径相对于纯软件实现取得了最高53.33$\times$的加速比，相对于CPU寄存器路径额外贡献了约3.6--3.8$\times$的效率提升。全部360个KAT测试用例逐字节比对NIST标准答案通过，Decaps隐式拒绝路径同样验证正确。
+
+\subsection{FFT测试结果}
+
+FFT加速器在SoC环境中完成了CPU寄存器路径和DMA路径两种模式的功能与性能测试。测试使用单一频率正弦波作为输入（1024点采样），硬件输出与软件参考FFT的逐bin比对结果验证了变换的正确性。表\ref{tab:fft_results}列出两种数据路径的性能对比。
+
+\begin{table}[htbp]
+\centering
+\caption{FFT加速器测试结果}
+\label{tab:fft_results}
+\begin{tabular}{lccc}
+\toprule
+\textbf{测试模式} & \textbf{耗时 (ms)} & \textbf{加速比} & \textbf{最大误差} \\
+\midrule
+CPU寄存器路径 & 1.724  & 142.55$\times$ & 1 (Re) / 2 (Im) \\
+DMA路径       & 0.293  & 838.32$\times$ & 1 (Re) / 2 (Im) \\
+\midrule
+软件参考 (33 MHz CPU) & 245.6 & — & — \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+CPU寄存器路径中，CPU逐字通过AXI寄存器写入1024个实部和虚部样本，启动FFT后轮询完成状态，再逐字回读输出结果，总耗时约1.72 ms（硬件计算+寄存器I/O），加速比为143×。DMA路径中，输入和输出数据全部通过DMA的mem2ep和ep2mem通道批量搬运，绕过了逐字AXI寄存器访问的开销，总耗时降至0.29 ms，加速比达到838×。两种路径的硬件输出与软件参考FFT的最大偏差仅为1（实部）和2（虚部），验证了16-bit定点FFT硬件实现的高精度。
+
+\subsection{系统时序收敛}
+
+完整SoC在Xilinx Artix-7 XC7A200T-1器件上完成布局布线，三个时钟域均通过时序收敛。主要时序指标如表\ref{tab:sys_timing}所示。
+
+\begin{table}[htbp]
+\centering
+\caption{SoC布局布线后时序收敛结果}
+\label{tab:sys_timing}
+\begin{tabular}{lccc}
+\toprule
+\textbf{时钟域} & \textbf{频率} & \textbf{Setup WNS} & \textbf{违例端点} \\
+\midrule
+cpu\_clk     & 33 MHz   & +0.737 ns & 0 / 17,197 \\
+mlkem\_clk   & 77 MHz   & +0.070 ns & 0 / 31,646 \\
+sys\_clk     & 50 MHz   & +0.125 ns & 0 / 22,307 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{系统资源利用}
+
+SoC整体资源利用见表\ref{tab:sys_util}。数据来自Vivado 2019.2布局布线后报告（器件XC7A200T-1，无DSP约束配置）。
+
+\begin{table}[htbp]
+\centering
+\caption{SoC整体资源利用}
+\label{tab:sys_util}
+\begin{tabular}{lccc}
+\toprule
+\textbf{资源} & \textbf{已用} & \textbf{可用} & \textbf{利用率} \\
+\midrule
+Slice LUTs（Total）   & 71,196 & 133,800 & 53.2\% \\
+Slice LUTs（Logic）   & 69,453 & 133,800 & 51.9\% \\
+Slice Registers       & 39,690 & 267,600 & 14.8\% \\
+Block RAM Tile        & 28.0   & 365     &  7.7\% \\
+~~RAMB36E1            & 10     & 365     &  2.7\% \\
+~~RAMB18E1            & 36     & 730     &  4.9\% \\
+DSP48E1               & 0      & 740     &  0.0\% \\
+BUFG                  & 4      & 32      & 12.5\% \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+表\ref{tab:module_util}给出按模块层次分解的资源利用明细，从中可以清晰看出各子系统在总体面积中的贡献比例。
+
+\begin{table}[htbp]
+\centering
+\footnotesize
+\caption{主要模块资源利用明细}
+\label{tab:module_util}
+\begin{tabular}{lrrrr}
+\toprule
+\textbf{模块} & \textbf{LUT} & \textbf{FF} & \textbf{BRAM} & \textbf{占比} \\
+\midrule
+ML-KEM              & 21,697 & 15,826 & 2$\times$36 + 14$\times$18 & 30.5\% \\
+~~FFT               &  6,949 &  1,083 & 8$\times$36 + 4$\times$18 &  9.8\% \\
+矩阵乘法             & 10,204 &  3,239 & —       & 14.3\% \\
+CPU (core\_top)     &  8,553 &  5,591 & 20$\times$18 & 12.0\% \\
+DMA/CDMA            &  1,558 &  1,476 & 1$\times$18  &  2.2\% \\
+Crossbar + CDC + 适配器 & 2,102 & 621 & —      &  3.0\% \\
+matmul序列桥        &    247 &    578 & —       &  0.3\% \\
+UART + confreg + DVI + SRAM & 1,711 & 1,222 & — & 2.4\% \\
+顶层胶合逻辑          &    812 &      4 & —       &  1.1\% \\
+\midrule
+\textbf{合计}        & \textbf{71,165} & \textbf{39,682} & \textbf{10$\times$36 + 31$\times$18} & \textbf{100\%} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+注：Vivado层次化报告中各子模块合计可能略小于顶层总数，原因在于跨层次LUT合并（cross-hierarchy LUT combining）机制。表中顶层总计为71,196 LUT。
+
+从模块资源分布可以得出以下观察。ML-KEM加速器消耗30.5\%的LUT，其ntt\_core采用双蝶形加4路Banked BRAM架构，poly\_mul\_sync的系数和中间数据缓冲亦通过BRAM实现，有效控制了LUT开销。矩阵乘法加速器以14.3\%的LUT占比位居第二，其4个并行32×32-bit流水线乘法器（每实例约1,000 LUT）是面积的主要贡献者。CPU核心消耗12.0\%的LUT，其中BTB（分支目标缓冲器）和TLB（地址转换旁路缓冲器）合占约3,000 LUT。FFT加速器虽仅占9.8\%的LUT，但消耗了最多的BRAM资源——8个RAMB36E1用于5级SDF架构中的延迟缓冲和旋转因子ROM存储。
+
+DSP使用量为零体现了竞赛规则约束和设计策略的一致性——ML-KEM不使用DSP、矩阵乘法受竞赛条款限制、FFT采用16-bit窄数据宽度，三者共同导致了全LUT乘法映射的设计决策。
+
+\subsection{功耗分析}
+
+布局布线后系统功耗的层次化分解如表\ref{tab:power}所示。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{系统功耗层次化分解}
+\label{tab:power}
+\begin{tabular}{lcc}
+\toprule
+\textbf{模块} & \textbf{动态功耗(W)} & \textbf{占动态功耗比} \\
+\midrule
+ML-KEM（u\_mlkem）        & 0.218 & 40.0\% \\
+PLL时钟生成器              & 0.138 & 25.3\% \\
+矩阵乘法（u\_matmul）      & 0.081 & 14.9\% \\
+FFT（u\_FFT）             & 0.027 &  5.0\% \\
+CPU（u\_cpu）             & 0.025 &  4.6\% \\
+DMA/CDMA                  & 0.008 &  1.5\% \\
+其它外设与总线              & 0.048 &  8.8\% \\
+\midrule
+\textbf{动态功耗合计}        & \textbf{0.545} & 100\% \\
+器件静态功耗                & 0.141 & — \\
+\midrule
+\textbf{总片上功耗}          & \textbf{0.686} & — \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+系统总功耗为0.686 W，其中动态功耗占79.4\%（0.545 W），静态功耗占20.6\%（0.141 W）。ML-KEM是最大的动态功耗来源（40.0\%），与资源利用分布一致。PLL以25.3\%的比例位居第二，反映了其驱动多时钟域（cpu\_clk、sys\_clk）的固有功耗开销。按资源类型划分，信号翻转功耗（0.194 W，占动态功耗35.6\%）和Slice Logic功耗（0.109 W，20.0\%）是两类最大的器件级功耗来源。
+
+\subsection{设计复杂度分析}
+
+表\ref{tab:complexity}列出主要模块的Rent指数和平均扇出数。Rent指数是衡量模块内部互联复杂度的指标，数值越低表示结构越规整、局部互联越密集。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{模块设计复杂度（Rent指数）}
+\label{tab:complexity}
+\begin{tabular}{lccr}
+\toprule
+\textbf{模块} & \textbf{Rent指数} & \textbf{平均扇出} & \textbf{总实例数} \\
+\midrule
+矩阵乘法器 & 0.60（Normal） & 3.76 & 15,711 \\
+CPU        & 0.59（Normal） & 3.96 & 15,822 \\
+UART       & 0.55（Normal） & 3.54 &  1,296 \\
+DMA/CDMA   & 0.46（Low）     & 3.31 &  3,435 \\
+ML-KEM     & 0.41（Low）     & 3.78 & 87,846 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+ML-KEM的Rent指数（0.41）在主要模块中最低，表明其数据通路具有高度规整的局部互联特性——多项式系数在相邻流水级之间传递，NTT蝶形单元按固定模式访问系数寄存器，这种结构化特征有利于布局布线的时序收敛。相比之下，矩阵乘法器和CPU的Rent指数较高（0.59--0.60），反映其控制逻辑的随机互联特性。FFT/ML-KEM共享从机以87,846个实例的规模（占全系统66.7\%的LUT实例数）成为物理设计中最庞大的层次化模块。
+
+\subsection{高扇出网络分析}
+
+表\ref{tab:fanout}列出布局布线后扇出最高的前5个网络，这些网络是潜在的时序瓶颈和布线拥塞来源。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{高扇出网络（Top 5）}
+\label{tab:fanout}
+\begin{tabular}{lcl}
+\toprule
+\textbf{网络名称} & \textbf{扇出} & \textbf{驱动源} \\
+\midrule
+sys\_clk（全局时钟）     & 35,652 & BUFG \\
+ML-KEM ek\_bram延迟寄存器 & 24,670 & LUT5 \\
+CPU复位网络              &  5,108 & LUT1 \\
+ML-KEM poly\_mul计数器   &  3,758 & FDCE \\
+matmul FSM独热状态        &  2,151 & FDRE \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+全局时钟网络（sys\_clk，BUFG驱动）以35,652个负载位居首位，在当前50 MHz工作频率下不构成时序问题。ML-KEM内部有两个高扇出网络进入前5名：系数存储BRAM的延迟寄存器链（24,670扇出）源于字节编码器中一个组合使能信号被复制到大量并行路径；多项式乘法模块的加载计数器（3,758扇出）属于多路复用地址总线的经典高扇出场景。这些网络在当前工作条件下均未产生时序违例。
+
+\subsection{验证结果汇总}
+
+表\ref{tab:verify_summary}给出系统级验证的覆盖范围和结果汇总。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{系统级验证结果汇总}
+\label{tab:verify_summary}
+\begin{tabular}{lcccl}
+\toprule
+\textbf{验证项} & \textbf{测试路径} & \textbf{迭代次数} & \textbf{通过率} & \textbf{关键指标} \\
+\midrule
+矩阵乘法 & CPU寄存器路径  & —    & 100\% & CRC32校验正确 \\
+矩阵乘法 & DMA序列控制器 & 10组  & 100\% & 总计213,060周期 \\
+ML-KEM   & SW/CPU/DMA三路径 & 100/级 & 100\% & KAT逐字节比对 \\
+FFT      & CPU寄存器路径  & 1次   & 100\% & max error ≤2, 143×加速比 \\
+FFT      & DMA路径        & 1次   & 100\% & max error ≤2, 838×加速比 \\
+DMA      & mem2mem        & 多次  & 100\% & 数据逐字比对 \\
+DMA      & mem2ep/ep2mem  & 多次  & 100\% & matmul Buffer读写正确 \\
+DMA      & 序列桥批量流水 & 10组  & 100\% & 全自动循环完成 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+% ================================================================
+\section{结论}
+
+本设计在龙芯SoC平台上成功构建了一个集成多种硬件加速器的异构计算系统。
+
+在AXI总线集成架构方面，以AXI交叉开关为核心互连部件，实现了CPU和DMA双主设备对8个从设备的统一地址空间访问，涵盖外部SRAM控制器、UART串口、DVI显示控制器、GPIO与定时器、DMA配置空间、FFT与ML-KEM共享加速窗口和矩阵乘法器。共享从机的内部二次路由设计——FFT与ML-KEM通过地址高位区分并共享同一端口——在不增加交叉开关端口数量的前提下实现了两种加速器的无缝共存，体现了在资源受限场景下灵活地址规划的工程价值。
+
+在DMA数据搬运体系方面，4通道CDMA控制器与matmul自动序列控制器的协同设计显著降低了CPU在批量计算任务中的参与度。序列控制器将逐组的源数据读取、矩阵计算触发、结果写回和组索引递增等操作固化为硬件状态机的自动循环，CPU仅需在批量任务启动前一次性配置6个序列参数。三条数据路径——mem2mem直接存储搬运、本地Endpoint加速器旁路通信和序列控制器的全自动批量流水——覆盖了SoC中所有的数据传输场景。
+
+在赛事任务完成度方面，矩阵乘法加速器严格遵循赛事规范：不使用DSP资源而全部以LUT逻辑实现32乘32-bit乘法；支持4乘4最大矩阵规模并兼容更小的非方阵规模（通过填零对齐）；输出结果按66-bit精度拆分为3个32-bit字的标准格式；输入输出数据布局完全符合128字节源组和192字节结果组的赛事定义。CRC32校验、批量序列测试和系统级仿真验证共同确认了加速器设计的完整正确性。
+
+在后量子密码硬件集成方面，ML-KEM加速器通过共享AXI从机与FFT复用Slave 6端口，在不增加Crossbar端口数量的前提下完整实现了FIPS 203标准的全部三种操作和三种安全等级的硬件加速。三路径诊断测试（软件参考、CPU寄存器、DMA窗口各100次迭代，覆盖ML-KEM-512/768/1024三种等级）全部通过，验证了IP核在真实SoC环境中的功能正确性和软硬件接口的长期运行稳定性。
+
+\begin{thebibliography}{10}
+
+\bibitem{loongson_soc}
+龙芯中科技术有限公司.
+\emph{龙芯杯全国大学生系统能力培养大赛——实验平台开发手册}.
+2024.
+
+\bibitem{fips203}
+National Institute of Standards and Technology.
+\emph{FIPS 203: Module-Lattice-Based Key-Encapsulation Mechanism Standard}.
+August 2024.
+
+\bibitem{artix7}
+Xilinx Inc.
+\emph{7 Series FPGAs Data Sheet: Overview (DS180)}.
+v2.6, 2020.
+
+\bibitem{vivado}
+Xilinx Inc.
+\emph{Vivado Design Suite User Guide: Synthesis (UG901)}.
+v2019.2, 2019.
+
+\bibitem{axi_spec}
+ARM Ltd.
+\emph{AMBA AXI and ACE Protocol Specification}.
+Issue H, 2013.
+
+\end{thebibliography}
+
+\end{document}

fpga/constraints/soc.xdc

@@ -227,10 +227,19 @@ set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 
-create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
+# create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
-create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
+# create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
 
-set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk]
+# set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk]
+
+create_generated_clock -name cpu_clk  [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
+create_generated_clock -name sys_clk  [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
+create_generated_clock -name mlkem_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2]
+
+set_clock_groups -asynchronous \
+    -group [get_clocks cpu_clk] \
+    -group [get_clocks sys_clk] \
+    -group [get_clocks mlkem_clk]
 
 set_input_delay -clock sys_clk -max 3   [get_ports {base_ram_data[*]}]
 set_input_delay -clock sys_clk -min 2   [get_ports {base_ram_data[*]}]

fpga/vivado_reports_nodsp/clock_interaction.rpt

@@ -1,28 +1,39 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:13 2026
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:55 2026
+=======
+| Date         : Sat Jul 11 09:20:56 2026
+>>>>>>> Stashed changes
 | Host         : fedora running 64-bit unknown
-| Command      : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt
+| Command      : report_clock_interaction -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clock_interaction.rpt
 | Design       : soc_top
 | Device       : 7a200t-fbg676
 | Speed File   : -1  PRODUCTION 1.23 2018-06-13
-------------------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------------------------------------------------
 
 Clock Interaction Report
 
 Clock Interaction Table
 -----------------------
 
-                                      WNS                            TNS Failing  TNS Total    WNS Path         Clock-Pair           Inter-Clock          
+                                    WNS                            TNS Failing  TNS Total    WNS Path         Clock-Pair           Inter-Clock          
-From Clock         To Clock           Clock Edges  WNS(ns)  TNS(ns)    Endpoints    Endpoints  Requirement(ns)  Classification       Constraints          
+From Clock        To Clock          Clock Edges  WNS(ns)  TNS(ns)    Endpoints    Endpoints  Requirement(ns)  Classification       Constraints          
------------------  -----------------  -----------  -------  -------  -----------  -----------  ---------------  -------------------  -------------------  
+----------------  ----------------  -----------  -------  -------  -----------  -----------  ---------------  -------------------  -------------------  
-cpu_clk            cpu_clk            rise - rise     2.72     0.00            0        17264            30.32  Clean                Timed                
+<<<<<<< Updated upstream
-cpu_clk            sys_clk                                                     0          162                   Ignored              Asynchronous Groups  
+cpu_clk           cpu_clk           rise - rise     1.51     0.00            0        17264            30.32  Clean                Timed                
-mlkem_clk_clk_pll  mlkem_clk_clk_pll  rise - rise    10.81     0.00            0        74168            40.00  Clean                Timed                
+cpu_clk           sys_clk                                                    0          154                   Ignored              Asynchronous Groups  
-mlkem_clk_clk_pll  sys_clk            rise - rise    11.25     0.00            0           61            20.00  Clean                Timed                
+sys_clk           cpu_clk                                                    0           59                   Ignored              Asynchronous Groups  
-sys_clk            cpu_clk                                                     0           59                   Ignored              Asynchronous Groups  
+sys_clk           sys_clk           rise - rise     0.15     0.00            0        96069            20.00  Clean                Timed                
-sys_clk            mlkem_clk_clk_pll  rise - rise     9.16     0.00            0          112            20.00  Clean                Timed                
+=======
-sys_clk            sys_clk            rise - rise     0.17     0.00            0        23704            20.00  Clean                Timed                
+cpu_clk           cpu_clk           rise - rise     0.74     0.00            0        17264            30.00  Clean                Timed                
+cpu_clk           sys_clk                                                    0          162                   Ignored              Asynchronous Groups  
+mlkem_clk         mlkem_clk         rise - rise     0.07     0.00            0        48386            13.00  Clean                Timed                
+mlkem_clk         sys_clk                                                    0           61                   Ignored              Asynchronous Groups  
+sys_clk           cpu_clk                                                    0           59                   Ignored              Asynchronous Groups  
+sys_clk           mlkem_clk                                                  0          112                   Ignored              Asynchronous Groups  
+sys_clk           sys_clk           rise - rise     0.12     0.00            0        23193            20.00  Clean                Timed                
+>>>>>>> Stashed changes
 
 

fpga/vivado_reports_nodsp/clocks.rpt

@@ -1,13 +1,17 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:13 2026
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:54 2026
+=======
+| Date         : Sat Jul 11 09:20:56 2026
+>>>>>>> Stashed changes
 | Host         : fedora running 64-bit unknown
-| Command      : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt
+| Command      : report_clocks -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clocks.rpt
 | Design       : soc_top
 | Device       : 7a200t-fbg676
 | Speed File   : -1  PRODUCTION 1.23 2018-06-13
---------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------------------------------
 
 Clock Report
 
@@ -21,12 +25,16 @@ Attributes
   I: Inverted
   S: Pin phase-shifted with Latency mode
 
-Clock              Period(ns)  Waveform(ns)    Attributes  Sources
+Clock             Period(ns)  Waveform(ns)    Attributes  Sources
-clk                20.000      {0.000 10.000}  P           {clk}
+clk               20.000      {0.000 10.000}  P           {clk}
-clkfbout_clk_pll   20.000      {0.000 10.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+clkfbout_clk_pll  20.000      {0.000 10.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
-cpu_clk            30.323      {0.000 15.161}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+<<<<<<< Updated upstream
-mlkem_clk_clk_pll  40.000      {0.000 20.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+cpu_clk           30.323      {0.000 15.161}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
-sys_clk            20.000      {0.000 10.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+=======
+cpu_clk           30.000      {0.000 15.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+mlkem_clk         13.000      {0.000 6.500}   P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+>>>>>>> Stashed changes
+sys_clk           20.000      {0.000 10.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
 
 
 ====================================================
@@ -43,16 +51,19 @@ Generated Clock     : cpu_clk
 Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
 Master Clock        : clk
 Edges               : {1 2 3}
-Edge Shifts(ns)     : {0.000 5.161 10.323}
+Edge Shifts(ns)     : {0.000 5.000 10.000}
 Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
 
-Generated Clock     : mlkem_clk_clk_pll
+<<<<<<< Updated upstream
+=======
+Generated Clock     : mlkem_clk
 Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
 Master Clock        : clk
 Edges               : {1 2 3}
-Edge Shifts(ns)     : {0.000 10.000 20.000}
+Edge Shifts(ns)     : {0.000 -3.500 -7.000}
 Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
 
+>>>>>>> Stashed changes
 Generated Clock     : sys_clk
 Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
 Master Clock        : clk

fpga/vivado_reports_nodsp/design_analysis_complexity.rpt

@@ -1,13 +1,17 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:35:00 2026
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:15:40 2026
+=======
+| Date         : Sat Jul 11 09:21:26 2026
+>>>>>>> Stashed changes
 | Host         : fedora running 64-bit unknown
-| Command      : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt
+| Command      : report_design_analysis -complexity -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt
 | Design       : soc_top
 | Device       : xc7a200t
 | Design State : Routed
--------------------------------------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
 
 Report Design Analysis
 
@@ -18,18 +22,31 @@ Table of Contents
 1. Complexity Characteristics (Cells)
 -------------------------------------
 
-+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
+<<<<<<< Updated upstream
-|          Instance         |        Module       | Rent | Average Fanout | Total Instances |    LUT1   |     LUT2    |     LUT3    |     LUT4    |     LUT5    |     LUT6     | Memory LUT | DSP | RAMB | MUXF | URAM |
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
-+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
+|          Instance         |        Module       | Rent | Average Fanout | Total Instances |    LUT1   |     LUT2    |     LUT3     |     LUT4     |     LUT5     |     LUT6     | Memory LUT | DSP | RAMB | MUXF | URAM |
-| (top)                     |             soc_top | 0.34 |           3.77 |          118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) |       1175 |  16 |   39 | 6020 |    0 |
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
-|  u_axi_axil_adapter       |    axi_axil_adapter | 0.50 |           5.92 |            1309 |   0(0.0%) |     8(0.7%) |    43(3.8%) |   100(8.9%) |  200(17.7%) |   776(68.9%) |          0 |   0 |    0 |    0 |    0 |
+| (top)                     |             soc_top | 0.31 |           3.78 |          131904 | 802(1.0%) | 9228(11.4%) | 10135(12.5%) | 10316(12.7%) | 12781(15.7%) | 37981(46.7%) |       1175 |   0 |   41 | 6069 |    0 |
-|  u_axi_uart_controller    | axi_uart_controller | 0.55 |           3.54 |            1296 |  10(1.2%) |   84(10.4%) |    80(9.9%) |  144(17.9%) |  194(24.1%) |   293(36.4%) |          0 |   0 |    0 |    9 |    0 |
+|  u_axi_axil_adapter       |    axi_axil_adapter | 0.37 |           4.65 |            1624 |   0(0.0%) |    25(1.8%) |     36(2.6%) |   860(61.8%) |   202(14.5%) |   269(19.3%) |          0 |   0 |    0 |   62 |    0 |
-|  u_cdma_matmul_bridge     |  cdma_matmul_bridge | 0.46 |           2.22 |            1002 |   1(0.3%) |   65(17.1%) |   39(10.3%) |  174(45.8%) |    13(3.4%) |    88(23.2%) |          0 |   0 |    0 |    0 |    0 |
+|  u_axi_uart_controller    | axi_uart_controller | 0.55 |           3.54 |            1296 |  10(1.2%) |   84(10.4%) |     80(9.9%) |   144(17.9%) |   194(24.1%) |   293(36.4%) |          0 |   0 |    0 |    9 |    0 |
-|  u_cpu                    |            core_top | 0.56 |           3.96 |           15822 | 168(1.8%) |   579(6.3%) | 1029(11.1%) |   871(9.4%) | 1744(18.9%) |  4860(52.5%) |          0 |   0 |   20 |  276 |    0 |
+|  u_cpu                    |            core_top | 0.59 |           3.96 |           15822 | 168(1.8%) |   579(6.3%) |  1029(11.1%) |    871(9.4%) |  1744(18.9%) |  4860(52.5%) |          0 |   0 |   20 |  276 |    0 |
-|  u_fft_mlkem_axi_slave    | fft_mlkem_axi_slave | 0.56 |           3.75 |           74954 | 362(0.9%) |  3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) |       1169 |  16 |   18 | 5286 |    0 |
+|  u_fft_mlkem_axi_slave    | fft_mlkem_axi_slave | 0.41 |           3.78 |           87846 | 374(0.7%) | 6103(11.5%) |  7425(14.0%) |  6353(12.0%) |  8174(15.5%) | 24445(46.2%) |       1169 |   0 |   20 | 5269 |    0 |
-|  u_matmul_axi_slave       |    matmul_axi_slave | 0.63 |           3.76 |           15159 |  18(0.2%) | 1646(15.2%) |   357(3.3%) |   830(7.6%) |   974(9.0%) |  7026(64.7%) |          6 |   0 |    0 |  413 |    0 |
+|  u_matmul_axi_slave       |    matmul_axi_slave | 0.60 |           3.76 |           15711 |  18(0.2%) | 1632(14.3%) |    345(3.0%) |    805(7.1%) |  1733(15.2%) |  6875(60.3%) |          6 |   0 |    0 |  417 |    0 |
-|  u_snix_axil_cdma_mux_8ch |  snix_axil_cdma_mux | 0.36 |           3.45 |            3680 | 136(6.5%) |   181(8.6%) |  405(19.3%) |  255(12.2%) |  342(16.3%) |   776(37.0%) |          0 |   0 |    1 |    4 |    0 |
+|  u_snix_axil_cdma_mux_8ch |  snix_axil_cdma_mux | 0.46 |           3.31 |            3435 | 136(7.4%) |  239(12.9%) |   432(23.4%) |   301(16.3%) |   234(12.6%) |   508(27.5%) |          0 |   0 |    1 |    4 |    0 |
-+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
+=======
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
+|          Instance         |        Module       | Rent | Average Fanout | Total Instances |    LUT1   |     LUT2    |     LUT3     |     LUT4    |     LUT5    |     LUT6     | Memory LUT | DSP | RAMB | MUXF | URAM |
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
+| (top)                     |             soc_top | 0.37 |           3.61 |          102050 | 871(1.4%) | 8543(13.4%) | 10370(16.3%) | 8684(13.7%) | 8274(13.0%) | 26800(42.2%) |       1216 |   0 |   49 | 2433 |    0 |
+|  u_axi_axil_adapter       |    axi_axil_adapter | 0.43 |           4.86 |            1534 |   0(0.0%) |    28(2.2%) |     37(2.8%) |  763(58.6%) |  216(16.6%) |   258(19.8%) |          0 |   0 |    0 |   62 |    0 |
+|  u_axi_uart_controller    | axi_uart_controller | 0.55 |           3.54 |            1296 |  10(1.2%) |   84(10.4%) |     80(9.9%) |  144(17.9%) |  194(24.1%) |   293(36.4%) |          0 |   0 |    0 |    9 |    0 |
+|  u_cpu                    |            core_top | 0.62 |           3.96 |           15822 | 168(1.8%) |   579(6.3%) |  1029(11.1%) |   871(9.4%) | 1744(18.9%) |  4860(52.5%) |          0 |   0 |   20 |  276 |    0 |
+|  u_fft_mlkem_axi_slave    | fft_mlkem_axi_slave | 0.35 |           3.49 |           58249 | 424(1.2%) | 5455(15.4%) |  7551(21.3%) | 4691(13.2%) | 4348(12.2%) | 13041(36.7%) |       1210 |   0 |   28 | 1632 |    0 |
+|  u_matmul_axi_slave       |    matmul_axi_slave | 0.58 |           3.76 |           15281 |  18(0.2%) | 1640(14.9%) |    369(3.4%) |   792(7.2%) |  1009(9.2%) |  7145(65.1%) |          6 |   0 |    0 |  418 |    0 |
+|  u_snix_axil_cdma_mux_8ch |  snix_axil_cdma_mux | 0.41 |           3.25 |            3423 | 136(7.4%) |  183(10.0%) |   430(23.4%) |  401(21.8%) |  243(13.2%) |   445(24.2%) |          0 |   0 |    1 |    4 |    0 |
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
+>>>>>>> Stashed changes
 * Complexity Ranges 
 ** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal,  0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
 *** -* -> Not computable as cell size is very small

fpga/vivado_reports_nodsp/design_analysis_timing.rpt

@@ -1,13 +1,17 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:29 2026
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:15:09 2026
+=======
+| Date         : Sat Jul 11 09:21:05 2026
+>>>>>>> Stashed changes
 | Host         : fedora running 64-bit unknown
-| Command      : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt
+| Command      : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt
 | Design       : soc_top
 | Device       : xc7a200t
 | Design State : Routed
------------------------------------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
 
 Report Design Analysis
 
@@ -18,35 +22,67 @@ Table of Contents
 1. Setup Path Characteristics 1-1
 ---------------------------------
 
-+---------------------------+------------------------------------------------------+
+<<<<<<< Updated upstream
-|      Characteristics      |                        Path #1                       |
++---------------------------+----------------------------------------------------------------------------------------+
-+---------------------------+------------------------------------------------------+
+|      Characteristics      |                                         Path #1                                        |
-| Requirement               |                                               20.000 |
++---------------------------+----------------------------------------------------------------------------------------+
-| Path Delay                |                                               15.605 |
+| Requirement               |                                                                                 20.000 |
-| Logic Delay               | 5.343(35%)                                           |
+| Path Delay                |                                                                                 15.529 |
-| Net Delay                 | 10.263(65%)                                          |
+| Logic Delay               | 6.868(45%)                                                                             |
-| Clock Skew                |                                               -3.858 |
+| Net Delay                 | 8.661(55%)                                                                             |
-| Slack                     |                                                0.167 |
+| Clock Skew                |                                                                                 -3.955 |
-| Clock Relationship        | Safely Timed                                         |
+| Slack                     |                                                                                  0.146 |
-| Logic Levels              |                                                    9 |
+| Clock Relationship        | Safely Timed                                                                           |
-| Routes                    |                                                    9 |
+| Logic Levels              |                                                                                     14 |
-| Logical Path              | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT |
+| Routes                    |                                                                                     12 |
-| Start Point Clock         | sys_clk                                              |
+| Logical Path              | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF |
-| End Point Clock           | sys_clk                                              |
+| Start Point Clock         | sys_clk                                                                                |
-| DSP Block                 | None                                                 |
+| End Point Clock           | sys_clk                                                                                |
-| BRAM                      | None                                                 |
+| DSP Block                 | None                                                                                   |
-| IO Crossings              |                                                    3 |
+| BRAM                      | None                                                                                   |
-| Config Crossings          |                                                    0 |
+| IO Crossings              |                                                                                      3 |
-| SLR Crossings             |                                                    0 |
+| Config Crossings          |                                                                                      0 |
-| PBlocks                   |                                                    0 |
+| SLR Crossings             |                                                                                      0 |
-| High Fanout               |                                                  130 |
+| PBlocks                   |                                                                                      0 |
-| Dont Touch                |                                                    0 |
+| High Fanout               |                                                                                     80 |
-| Mark Debug                |                                                    0 |
+| Dont Touch                |                                                                                      0 |
-| Start Point Pin Primitive | FDRE/C                                               |
+| Mark Debug                |                                                                                      0 |
-| End Point Pin Primitive   | ext_ram_data[18]                                     |
+| Start Point Pin Primitive | FDCE/C                                                                                 |
-| Start Point Pin           | FSM_sequential_ext_wr_state_reg[1]/C                 |
+| End Point Pin Primitive   | base_ram_be_n[3]                                                                       |
-| End Point Pin             | ext_ram_data[18]                                     |
+| Start Point Pin           | ax_req_q_len_reg[3]/C                                                                  |
-+---------------------------+------------------------------------------------------+
+| End Point Pin             | base_ram_be_n[3]                                                                       |
++---------------------------+----------------------------------------------------------------------------------------+
+=======
++---------------------------+-----------------------+
+|      Characteristics      |        Path #1        |
++---------------------------+-----------------------+
+| Requirement               |                13.000 |
+| Path Delay                |                13.035 |
+| Logic Delay               | 0.752(6%)             |
+| Net Delay                 | 12.283(94%)           |
+| Clock Skew                |                 0.135 |
+| Slack                     |                 0.070 |
+| Clock Relationship        | Safely Timed          |
+| Logic Levels              |                     1 |
+| Routes                    |                     1 |
+| Logical Path              | FDRE MUXF7 FDCE       |
+| Start Point Clock         | mlkem_clk             |
+| End Point Clock           | mlkem_clk             |
+| DSP Block                 | None                  |
+| BRAM                      | None                  |
+| IO Crossings              |                     0 |
+| Config Crossings          |                     0 |
+| SLR Crossings             |                     0 |
+| PBlocks                   |                     0 |
+| High Fanout               |                  1088 |
+| Dont Touch                |                     0 |
+| Mark Debug                |                     0 |
+| Start Point Pin Primitive | FDRE/C                |
+| End Point Pin Primitive   | FDCE/D                |
+| Start Point Pin           | dj_wb_inz_reg/C       |
+| End Point Pin             | dj_block_r_reg[732]/D |
++---------------------------+-----------------------+
+>>>>>>> Stashed changes
 * Bounding box calculated as % of dimensions for the target device (436, 500)
 
 

fpga/vivado_reports_nodsp/drc.rpt

@@ -1,14 +1,18 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:33:58 2026
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:40 2026
+=======
+| Date         : Sat Jul 11 09:20:47 2026
+>>>>>>> Stashed changes
 | Host         : fedora running 64-bit unknown
-| Command      : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt
+| Command      : report_drc -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/drc.rpt
 | Design       : soc_top
 | Device       : xc7a200tfbg676-1
 | Speed File   : -1
 | Design State : Fully Routed
-------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------------------------
 
 Report DRC
 
@@ -24,14 +28,11 @@ Table of Contents
       Design limits: <entire design considered>
            Ruledeck: default
              Max violations: <unlimited>
-             Violations found: 90
+             Violations found: 42
 +-----------+----------+----------------------------+------------+
 | Rule      | Severity | Description                | Violations |
 +-----------+----------+----------------------------+------------+
 | CHECK-3   | Warning  | Report rule limit reached  | 2          |
-| DPIP-1    | Warning  | Input pipelining           | 16         |
-| DPOP-1    | Warning  | PREG Output pipelining     | 16         |
-| DPOP-2    | Warning  | MREG Output pipelining     | 16         |
 | REQP-1839 | Warning  | RAMB36 async control check | 20         |
 | REQP-1840 | Warning  | RAMB18 async control check | 20         |
 +-----------+----------+----------------------------+------------+
@@ -48,246 +49,6 @@ Report rule limit reached
 REQP-1840 rule limit reached: 20 violations have been found.
 Related violations: <none>
 
-DPIP-1#1 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#2 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#3 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#4 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#5 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#6 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#7 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#8 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#9 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#10 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#11 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#12 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#13 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#14 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#15 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#16 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPOP-1#1 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#2 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#3 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#4 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#5 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#6 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#7 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#8 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#9 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#10 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#11 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#12 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#13 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#14 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#15 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#16 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-2#1 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#2 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#3 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#4 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#5 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#6 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#7 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#8 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#9 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#10 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#11 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#12 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#13 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#14 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#15 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#16 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
 REQP-1839#1 Warning
 RAMB36 async control check  
 The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.

fpga/vivado_reports_nodsp/high_fanout.rpt

@@ -1,12 +1,16 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:13 2026
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:55 2026
+=======
+| Date         : Sat Jul 11 09:20:57 2026
+>>>>>>> Stashed changes
 | Host         : fedora running 64-bit unknown
-| Command      : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt
+| Command      : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/high_fanout.rpt
 | Design       : soc_top
 | Device       : xc7a200t
---------------------------------------------------------------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 
 High Fan-out Nets Information
 
@@ -16,132 +20,133 @@ High Fan-out Nets Information
 +---------------------------------------------------------------------------------------+--------+-------------+
 | Net Name                                                                              | Fanout | Driver Type |
 +---------------------------------------------------------------------------------------+--------+-------------+
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1]                |  24598 | LUT5        |
+<<<<<<< Updated upstream
-| pll_clk.u_clk_pll/inst/sys_clk                                                        |  10004 | BUFG        |
+| pll_clk.u_clk_pll/inst/sys_clk                                                        |  35652 | BUFG        |
-| pll_clk.u_rst_sys/p_0_in                                                              |   4130 | LUT1        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1]                |  24670 | LUT5        |
+| pll_clk.u_rst_sys/p_0_in                                                              |   5108 | LUT1        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[0]                    |   3758 | FDCE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0                                        |   2151 | FDRE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/delay_reg[1]               |  15647 | LUT5        |
+| pll_clk.u_clk_pll/inst/sys_clk                                                        |   9971 | BUFG        |
+| pll_clk.u_rst_sys/p_0_in                                                              |   4121 | LUT1        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mb_en                   |   2121 | LUT6        |
+>>>>>>> Stashed changes
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0]                         |   2048 | LUT2        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[0]_0                                        |   2018 | FDSE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0               |   1619 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0        |   1613 | LUT3        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0]              |   1608 | LUT2        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0               |   1608 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 |   1604 | LUT5        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd                      |   1603 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0        |   1601 | LUT3        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0           |   1601 | LUT6        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0           |   1601 | LUT6        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0           |   1601 | LUT6        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0       |   1600 | LUT4        |
+<<<<<<< Updated upstream
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1]                   |   1543 | FDCE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2]                   |   1542 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active                             |   1130 | FDCE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1                 |   1109 | LUT2        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0                     |   1088 | FDRE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0                     |   1088 | FDRE        |
-| pll_clk.u_rst_mlkem/delay_reg[1]_0                                                    |   1069 | LUT1        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0                           |    938 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0                           |    936 | LUT5        |
+| u_matmul_axi_slave/w_addr[2]                                                          |    873 | FDRE        |
 | u_cpu/reset                                                                           |    799 | FDRE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0]  |    769 | CARRY4      |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1]  |    769 | CARRY4      |
-| u_matmul_axi_slave/w_addr[2]                                                          |    724 | FDRE        |
 | u_cpu/u_mul/E[0]                                                                      |    716 | LUT1        |
-| u_matmul_axi_slave/w_addr[3]                                                          |    628 | FDRE        |
+| u_matmul_axi_slave/w_addr[4]                                                          |    655 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1                                  |    528 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1                                  |    525 | LUT6        |
-| u_matmul_axi_slave/current_r_offset[2]                                                |    522 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1]                   |    518 | FDCE        |
-| u_matmul_axi_slave/current_r_offset[3]                                                |    520 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0]                   |    515 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0]                   |    516 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1]                   |    516 | FDCE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0              |    512 | LUT2        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0]             |    512 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[3]_0[0]                 |    512 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2]             |    390 | FDCE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2]  |    385 | CARRY4      |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0                      |    370 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in                     |   1344 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1                 |   1109 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0                     |   1088 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0                     |   1088 | FDRE        |
+| pll_clk.u_rst_mlkem/delay_reg[1]_1                                                    |   1066 | LUT1        |
+| u_cpu/reset                                                                           |    799 | FDRE        |
+| u_cpu/u_mul/E[0]                                                                      |    716 | LUT1        |
+| u_matmul_axi_slave/w_addr[2]                                                          |    644 | FDRE        |
+| u_matmul_axi_slave/current_r_offset[2]                                                |    524 | LUT5        |
+| u_matmul_axi_slave/current_r_offset[3]                                                |    522 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[2]_rep__3[0]            |    513 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0              |    512 | LUT2        |
+>>>>>>> Stashed changes
 | u_cpu/wb_stage/w_index[0]                                                             |    358 | LUT6        |
 | u_cpu/wb_stage/w_index[1]                                                             |    358 | LUT6        |
 | u_cpu/wb_stage/w_index[2]                                                             |    358 | LUT6        |
 | u_cpu/wb_stage/w_index[3]                                                             |    358 | LUT6        |
 | u_cpu/wb_stage/w_index[4]                                                             |    358 | LUT6        |
+| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 |    357 | LUT3        |
+| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0                                                |    356 | LUT3        |
 | u_matmul_axi_slave/acc_idx_d4[0]                                                      |    354 | FDRE        |
 | u_matmul_axi_slave/acc_idx_d4[1]                                                      |    354 | FDRE        |
 | u_matmul_axi_slave/acc_idx_d4[2]                                                      |    354 | FDRE        |
 | u_matmul_axi_slave/acc_idx_d4[3]                                                      |    354 | FDRE        |
 | u_cpu/wb_stage/we_0                                                                   |    324 | LUT4        |
-| u_matmul_axi_slave/w_addr[4]                                                          |    317 | FDRE        |
+<<<<<<< Updated upstream
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1                         |    290 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1                         |    293 | LUT6        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3]                      |    284 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[4]                             |    288 | CARRY4      |
-| u_matmul_axi_slave/cur_bank_reg_n_0                                                   |    277 | FDRE        |
+| u_matmul_axi_slave/cur_bank_reg_n_0                                                   |    274 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10]                  |    263 | RAMB18E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11]                  |    263 | RAMB18E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8]                   |    262 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7]                   |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9]                   |    261 | RAMB18E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10]                   |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11]                   |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9]                    |    261 | RAMB36E1    |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc                      |    261 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4]                    |    260 | FDCE        |
+| u_matmul_axi_slave/sel0[1]                                                            |    259 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0]                   |    259 | RAMB36E1    |
+| u_matmul_axi_slave/b1_b_reg[0][31]_i_8_n_7                                            |    258 | CARRY4      |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1]                   |    259 | RAMB36E1    |
+| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0                                            |    258 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10]                 |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11]                 |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2]                  |    256 | FDCE        |
-| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0                                            |    259 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3]                  |    256 | FDCE        |
-| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0                                            |    257 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10]                   |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11]                   |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10]                 |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11]                 |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4]                  |    256 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0]        |    256 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_0[0]           |    256 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r                    |    256 | LUT3        |
-| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0                                              |    256 | LUT6        |
+| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0                                              |    256 | LUT6        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode                    |    250 | LUT4        |
-| u_matmul_axi_slave/w_addr[5]                                                          |    246 | FDRE        |
+| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge                                  |    245 | LUT2        |
+| u_matmul_axi_slave/b0_a[6][25]_i_2_n_0                                                |    242 | LUT2        |
+| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 |    239 | LUT3        |
+| u_matmul_axi_slave/m_in_a[3][30]_i_6_n_0                                              |    238 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6]                      |    237 | FDCE        |
+| u_cpu/exe_stage/ds_to_es_bus_r0                                                       |    234 | LUT5        |
+| u_cpu/mem_stage/E[0]                                                                  |    234 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3]                      |    231 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1                         |    289 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_4                |    288 | CARRY4      |
+| u_matmul_axi_slave/w_addr[4]                                                          |    286 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc                      |    260 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/E[0]                           |    256 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r                    |    256 | LUT3        |
+| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0                                              |    256 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode                    |    250 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_7                      |    248 | FDCE        |
 | u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge                                  |    245 | LUT3        |
 | u_cpu/exe_stage/ds_to_es_bus_r0                                                       |    234 | LUT5        |
 | u_cpu/mem_stage/E[0]                                                                  |    234 | LUT6        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0]                  |    234 | FDCE        |
+>>>>>>> Stashed changes
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10]                 |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11]                 |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10]                 |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11]                 |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9]                  |    234 | FDCE        |
-| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 |    229 | LUT3        |
-| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0                                              |    228 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1]                      |    227 | FDCE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0              |    224 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0               |    224 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0               |    224 | LUT4        |
@@ -150,72 +155,252 @@ High Fan-out Nets Information
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0               |    224 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0               |    224 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0               |    224 | LUT4        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10]                   |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11]                   |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[5]                      |    219 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10]                  |    216 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11]                  |    216 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8]                   |    215 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[2]                      |    215 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7]                   |    214 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9]                   |    214 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4]                      |    214 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6]                   |    212 | RAMB36E1    |
 | u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0                            |    211 | LUT2        |
 | u_cpu/mem_stage/es_to_ms_bus_r0                                                       |    210 | LUT2        |
 | u_cpu/u_csr/tlbw_r_tlbidx[2]                                                          |    210 | FDRE        |
-| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0]                                           |    203 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7]                      |    207 | FDCE        |
-| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1]                                           |    203 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1]                      |    206 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6]                      |    200 | FDCE        |
+=======
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4]                      |    200 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_2                      |    222 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3]             |    197 | FDCE        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0                            |    211 | LUT2        |
+| u_cpu/mem_stage/es_to_ms_bus_r0                                                       |    210 | LUT2        |
+| u_cpu/u_csr/tlbw_r_tlbidx[2]                                                          |    210 | FDRE        |
+>>>>>>> Stashed changes
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2]           |    196 | FDCE        |
-| u_snix_axil_cdma_mux_8ch/ADDRA[0]                                                     |    196 | LUT6        |
 | u_cpu/wb_stage/Q[33]                                                                  |    194 | FDRE        |
 | u_cpu/wb_stage/Q[34]                                                                  |    194 | FDRE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5]             |    194 | FDCE        |
+<<<<<<< Updated upstream
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3]  |    193 | CARRY4      |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0          |    191 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3]                            |    187 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2]                     |    187 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2]                    |    186 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3]                     |    187 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1]                      |    187 | FDCE        |
-| u_matmul_axi_slave/current_r_offset[4]                                                |    187 | LUT5        |
-| u_matmul_axi_slave/s_axi_wready_reg_1                                                 |    181 | LUT3        |
 | u_cpu/wb_stage/ws_valid_reg_0                                                         |    180 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3]                      |    180 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2]                             |    180 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2]                             |    177 | FDCE        |
+| u_matmul_axi_slave/b0_b_reg[1][30]_i_4_n_7                                            |    178 | CARRY4      |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0]                      |    176 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]                                 |    176 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[2]_rep_n_0                         |    191 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_6        |    186 | FDCE        |
+| u_matmul_axi_slave/w_addr[5]                                                          |    184 | FDRE        |
+| u_cpu/wb_stage/ws_valid_reg_0                                                         |    180 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_1        |    179 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2]                             |    178 | FDCE        |
+| u_matmul_axi_slave/b1_b[0][31]_i_7_n_0                                                |    177 | LUT3        |
+>>>>>>> Stashed changes
 | u_matmul_axi_slave/p_0_in__0                                                          |    176 | LUT4        |
 | u_matmul_axi_slave/p_0_in__0__0                                                       |    176 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt114_out                |    175 | LUT2        |
 | u_cpu/wb_stage/Q[37]                                                                  |    173 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7]                      |    173 | FDCE        |
+<<<<<<< Updated upstream
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7                     |    171 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]_rep__0_n_0     |    172 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[131][11]_i_4_n_0         |    171 | LUT3        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0                |    169 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0                |    169 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0                |    169 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0                |    169 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]                                 |    169 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[3]                             |    169 | CARRY4      |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5]                    |    166 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[74][11]_i_4_n_0          |    168 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[6]_0[0]                            |    168 | CARRY4      |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0                |    167 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_1                |    167 | LUT2        |
+| u_snix_axil_cdma_mux_8ch/ADDRA[0]                                                     |    167 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[129][11]_i_3_n_0         |    166 | LUT3        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__0_n_0                               |    165 | FDRE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_2        |    172 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_5                |    171 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/z_word_reg[1][31]_i_6_n_7                     |    170 | CARRY4      |
+| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0                                                |    170 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_4        |    168 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/z_word_reg[1][31]_i_6_n_6                     |    168 | CARRY4      |
+>>>>>>> Stashed changes
 | u_cpu/wb_stage/Q[32]                                                                  |    164 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0]                      |    164 | FDCE        |
 | u_cpu/wb_stage/Q[35]                                                                  |    163 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg[0]_rep__0_n_0             |    163 | FDCE        |
 | u_cpu/wb_stage/Q[36]                                                                  |    162 | FDRE        |
-| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0                |    161 | LUT3        |
+<<<<<<< Updated upstream
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0               |    160 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0                |    160 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0                |    160 | LUT4        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0                |    160 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__12_n_0    |    158 | FDCE        |
+| u_matmul_axi_slave/w_addr_reg[3]_rep__2_0                                             |    158 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[181][5]_i_3_n_0              |    157 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[6]                    |    156 | FDCE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3]                             |    155 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6]                     |    153 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[7]                    |    155 | FDCE        |
-| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0                                                |    153 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3]                      |    154 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4]                      |    154 | FDCE        |
+| u_matmul_axi_slave/w_addr[3]                                                          |    153 | FDRE        |
+=======
+| u_matmul_axi_slave/pipe_cnt_reg_n_0_[3]                                               |    162 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_34_n_0                      |    161 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3]                            |    158 | FDRE        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0                |    157 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3]                             |    156 | FDCE        |
+| u_matmul_axi_slave/w_addr_reg[3]_rep_n_0                                              |    153 | FDRE        |
+>>>>>>> Stashed changes
 | u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0                           |    151 | FDRE        |
 | u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1                                |    150 | CARRY4      |
 | u_cpu/dcache/awaddr[31]_i_3_n_0                                                       |    148 | LUT2        |
 | u_cpu/dcache/awaddr[31]_i_4_n_0                                                       |    148 | LUT2        |
-| u_matmul_axi_slave/s_axi_wready_reg_0                                                 |    148 | LUT5        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1]                      |    148 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[202][11]_i_3_n_0         |    148 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0]                      |    147 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__1_n_0     |    146 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep_n_0        |    146 | FDCE        |
+| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0                                                |    146 | LUT3        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0]                  |    145 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0                    |    144 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__10_n_0    |    145 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6]                            |    143 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2]                      |    144 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6]                      |    143 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[247]_i_3_n_0             |    144 | LUT4        |
-| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0                                                |    143 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[255]_i_3_n_0             |    144 | LUT4        |
-| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0                                                |    143 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__17_n_0    |    143 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0                     |    142 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[106][11]_i_3_n_0         |    143 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4]                            |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6]                            |    142 | FDCE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0]                                     |    142 | FDSE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5]                      |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5]                    |    141 | FDCE        |
 | u_cpu/dcache/write_buffer_state                                                       |    140 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0              |    140 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4]                            |    140 | FDCE        |
 | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5]                            |    140 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7]                            |    140 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN                        |    148 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_10       |    146 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_9        |    143 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]                                 |    142 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_43_n_0                      |    141 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_57_n_0                    |    141 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[4]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[5]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[6]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[7]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6]                            |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7]                            |    141 | FDCE        |
+| u_cpu/dcache/write_buffer_state                                                       |    140 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4]                            |    140 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__3_n_0                  |    140 | FDCE        |
 | u_cpu/u_csr/tlbw_r_tlbidx[0]                                                          |    139 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0                      |    139 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5]                            |    139 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0                  |    139 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_3                      |    138 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[3]                  |    138 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[6]_rep_n_0                |    138 | FDCE        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_1                |    137 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[4]_rep_n_0                |    137 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[5]_rep_n_0                |    137 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[2]                            |    137 | FDRE        |
+| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0                                            |    137 | FDRE        |
+| u_cpu/u_csr/tlbw_r_tlbidx[1]                                                          |    136 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1080]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1081]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1082]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1083]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1084]_i_6_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_3_n_0              |    136 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_9_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1087]_i_3_n_0               |    136 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[7]_rep_n_0                |    136 | FDCE        |
+| u_matmul_axi_slave/b1_b[0][31]_i_8_n_0                                                |    136 | LUT2        |
+| u_snix_axil_cdma_mux_8ch/ep_rd_elem[0]                                                |    136 | LUT6        |
+| u_snix_axil_cdma_mux_8ch/ep_rd_elem[1]                                                |    136 | LUT5        |
+| u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]                                                |    135 | LUT6        |
+| u_snix_axil_cdma_mux_8ch/ep_rd_elem[3]                                                |    135 | LUT5        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0                |    134 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_0                |    134 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_2                |    134 | LUT2        |
+| u_matmul_axi_slave/w_addr[3]                                                          |    134 | FDRE        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[29]_i_7_n_0                  |    133 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[29]_i_9_n_0                  |    133 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[31]_i_12_n_0                 |    133 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[31]_i_13_n_0                 |    133 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[3]_0                |    133 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/dbg_dk_idx[4]                                 |    133 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/dbg_dk_idx[3]                                 |    132 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_4                      |    132 | FDCE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[2]                                     |    132 | FDRE        |
+| u_matmul_axi_slave/c1_elem[0]                                                         |    132 | LUT6        |
+| u_matmul_axi_slave/c1_elem[1]                                                         |    132 | LUT5        |
+| u_matmul_axi_slave/c1_elem[2]                                                         |    132 | LUT4        |
+| u_matmul_axi_slave/c1_elem[3]                                                         |    132 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep_n_0                     |    131 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_reject                            |    130 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_8        |    130 | FDCE        |
+| u_matmul_axi_slave/pipe_cnt_reg_n_0_[1]                                               |    130 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[1]                                     |    129 | FDRE        |
+| u_confreg/s_rdata[31]_i_8_n_0                                                         |    128 | LUT3        |
+| u_confreg/s_rdata[31]_i_9_n_0                                                         |    128 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_reject_reg_rep_n_0                |    128 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0]                  |    128 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[1]                  |    128 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[2]                  |    128 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[4]             |    128 | FDCE        |
+| u_matmul_axi_slave/current_r_offset[5]                                                |    128 | LUT3        |
+| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0                                            |    128 | FDRE        |
+| u_matmul_axi_slave/pipe_cnt_reg_n_0_[0]                                               |    128 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__0_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__10_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__1_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__2_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__3_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__4_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__5_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__6_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__7_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__8_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__9_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep_n_0                                  |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__10_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__11_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__12_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__13_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__2_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__3_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__4_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__5_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__6_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__7_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__8_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__9_n_0                               |    127 | FDRE        |
+| u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]                                           |    127 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__0_n_0                  |    126 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__1_n_0                  |    126 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__2_n_0                  |    126 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_3        |    126 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/state[1]                        |    126 | FDCE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__11_0                                |    126 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__1_n_0                               |    126 | FDRE        |
+| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0]                                           |    126 | FDRE        |
+>>>>>>> Stashed changes
 +---------------------------------------------------------------------------------------+--------+-------------+
 
 

fpga/vivado_reports_nodsp/methodology.rpt

@@ -1,14 +1,18 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:05 2026
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:46 2026
+=======
+| Date         : Sat Jul 11 09:20:51 2026
+>>>>>>> Stashed changes
 | Host         : fedora running 64-bit unknown
-| Command      : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt
+| Command      : report_methodology -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/methodology.rpt
 | Design       : soc_top
 | Device       : xc7a200tfbg676-1
 | Speed File   : -1
 | Design State : Fully Routed
-------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------------------------------------
 
 Report Methodology
 
@@ -23,17 +27,27 @@ Table of Contents
           Floorplan: impl_1
       Design limits: <entire design considered>
              Max violations: <unlimited>
-             Violations found: 99
+<<<<<<< Updated upstream
+             Violations found: 107
+=======
+             Violations found: 115
+>>>>>>> Stashed changes
 +-----------+----------+-------------------------------------------------------------------+------------+
 | Rule      | Severity | Description                                                       | Violations |
 +-----------+----------+-------------------------------------------------------------------+------------+
 | LUTAR-1   | Warning  | LUT drives async reset alert                                      | 1          |
 | SYNTH-5   | Warning  | Mapped onto distributed RAM because of timing constraints         | 8          |
-| SYNTH-6   | Warning  | Timing of a block RAM might be sub-optimal                        | 1          |
+<<<<<<< Updated upstream
+| SYNTH-6   | Warning  | Timing of a block RAM might be sub-optimal                        | 9          |
 | SYNTH-16  | Warning  | Address collision                                                 | 8          |
+=======
+| SYNTH-6   | Warning  | Timing of a block RAM might be sub-optimal                        | 6          |
+| SYNTH-16  | Warning  | Address collision                                                 | 16         |
+| TIMING-9  | Warning  | Unknown CDC Logic                                                 | 1          |
+>>>>>>> Stashed changes
 | TIMING-10 | Warning  | Missing property on synchronizer                                  | 1          |
 | TIMING-18 | Warning  | Missing input or output delay                                     | 76         |
-| TIMING-47 | Warning  | False path or asynchronous clock group between synchronous clocks | 2          |
+| TIMING-47 | Warning  | False path or asynchronous clock group between synchronous clocks | 4          |
 | XDCC-1    | Warning  | Scoped Clock constraint overwritten with the same name            | 1          |
 | XDCC-7    | Warning  | Scoped Clock constraint overwritten on the same source            | 1          |
 +-----------+----------+-------------------------------------------------------------------+------------+
@@ -42,7 +56,11 @@ Table of Contents
 -----------------
 LUTAR-1#1 Warning
 LUT drives async reset alert  
-LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
+<<<<<<< Updated upstream
+LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24656 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
+=======
+LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 15633 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
+>>>>>>> Stashed changes
 Related violations: <none>
 
 SYNTH-5#1 Warning
@@ -87,7 +105,71 @@ Related violations: <none>
 
 SYNTH-6#1 Warning
 Timing of a block RAM might be sub-optimal  
-The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#2 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#3 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#4 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#5 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#6 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+Related violations: <none>
+
+SYNTH-6#7 Warning
+Timing of a block RAM might be sub-optimal  
+The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+Related violations: <none>
+
+SYNTH-6#8 Warning
+Timing of a block RAM might be sub-optimal  
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+Related violations: <none>
+
+SYNTH-6#9 Warning
+Timing of a block RAM might be sub-optimal  
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
 Related violations: <none>
 
 SYNTH-16#1 Warning
@@ -130,6 +212,51 @@ Address collision
 Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
 Related violations: <none>
 
+SYNTH-16#9 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#10 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#11 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#12 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#13 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#14 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#15 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#16 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+TIMING-9#1 Warning
+Unknown CDC Logic  
+One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities
+Related violations: <none>
+
 TIMING-10#1 Warning
 Missing property on synchronizer  
 One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
@@ -517,12 +644,22 @@ Related violations: <none>
 
 TIMING-47#1 Warning
 False path or asynchronous clock group between synchronous clocks  
-A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
+A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
 Related violations: <none>
 
 TIMING-47#2 Warning
 False path or asynchronous clock group between synchronous clocks  
-A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
+A Clock Group timing constraint is set between synchronous clocks mlkem_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
+Related violations: <none>
+
+TIMING-47#3 Warning
+False path or asynchronous clock group between synchronous clocks  
+A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
+Related violations: <none>
+
+TIMING-47#4 Warning
+False path or asynchronous clock group between synchronous clocks  
+A Clock Group timing constraint is set between synchronous clocks sys_clk and mlkem_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
 Related violations: <none>
 
 XDCC-1#1 Warning

fpga/vivado_reports_nodsp/power.rpt

@@ -1,16 +1,20 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date             : Wed Jul  8 03:34:25 2026
+<<<<<<< Updated upstream
+| Date             : Fri Jul 10 04:15:05 2026
+=======
+| Date             : Sat Jul 11 09:21:02 2026
+>>>>>>> Stashed changes
 | Host             : fedora running 64-bit unknown
-| Command          : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt
+| Command          : report_power -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/power.rpt
 | Design           : soc_top
 | Device           : xc7a200tfbg676-1
 | Design State     : routed
 | Grade            : commercial
 | Process          : typical
 | Characterization : Production
-------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------------------------------------
 
 Power Report
 
@@ -30,14 +34,25 @@ Table of Contents
 ----------
 
 +--------------------------+--------------+
-| Total On-Chip Power (W)  | 0.549        |
+<<<<<<< Updated upstream
+| Total On-Chip Power (W)  | 0.686        |
 | Design Power Budget (W)  | Unspecified* |
 | Power Budget Margin (W)  | NA           |
-| Dynamic (W)              | 0.409        |
+| Dynamic (W)              | 0.545        |
 | Device Static (W)        | 0.141        |
 | Effective TJA (C/W)      | 1.9          |
-| Max Ambient (C)          | 84.0         |
+| Max Ambient (C)          | 83.7         |
-| Junction Temperature (C) | 26.0         |
+| Junction Temperature (C) | 26.3         |
+=======
+| Total On-Chip Power (W)  | 0.779        |
+| Design Power Budget (W)  | Unspecified* |
+| Power Budget Margin (W)  | NA           |
+| Dynamic (W)              | 0.637        |
+| Device Static (W)        | 0.142        |
+| Effective TJA (C/W)      | 1.9          |
+| Max Ambient (C)          | 83.5         |
+| Junction Temperature (C) | 26.5         |
+>>>>>>> Stashed changes
 | Confidence Level         | Low          |
 | Setting File             | ---          |
 | Simulation Activity File | ---          |
@@ -52,22 +67,39 @@ Table of Contents
 +--------------------------+-----------+----------+-----------+-----------------+
 | On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
 +--------------------------+-----------+----------+-----------+-----------------+
-| Clocks                   |     0.042 |        7 |       --- |             --- |
+<<<<<<< Updated upstream
-| Slice Logic              |     0.069 |   120086 |       --- |             --- |
+| Clocks                   |     0.056 |        6 |       --- |             --- |
-|   LUT as Logic           |     0.064 |    63754 |    133800 |           47.65 |
+| Slice Logic              |     0.109 |   133224 |       --- |             --- |
-|   CARRY4                 |     0.002 |     2859 |     33450 |            8.55 |
+|   LUT as Logic           |     0.102 |    75460 |    133800 |           56.40 |
-|   LUT as Distributed RAM |    <0.001 |      740 |     46200 |            1.60 |
+|   CARRY4                 |     0.003 |     3546 |     33450 |           10.60 |
-|   Register               |    <0.001 |    39931 |    267600 |           14.92 |
+|   LUT as Distributed RAM |     0.002 |      628 |     46200 |            1.36 |
+|   Register               |     0.001 |    39690 |    267600 |           14.83 |
 |   LUT as Shift Register  |    <0.001 |     1175 |     46200 |            2.54 |
-|   F7/F8 Muxes            |    <0.001 |     6036 |    133800 |            4.51 |
+|   F7/F8 Muxes            |    <0.001 |     6085 |    133800 |            4.55 |
-|   Others                 |     0.000 |      318 |       --- |             --- |
+|   Others                 |     0.000 |      289 |       --- |             --- |
-| Signals                  |     0.115 |    85084 |       --- |             --- |
+| Signals                  |     0.194 |    93202 |       --- |             --- |
-| Block RAM                |     0.019 |     23.5 |       365 |            6.44 |
+| Block RAM                |     0.019 |     25.5 |       365 |            6.99 |
-| PLL                      |     0.132 |        1 |        10 |           10.00 |
+| PLL                      |     0.137 |        1 |        10 |           10.00 |
-| DSPs                     |     0.009 |       16 |       740 |            2.16 |
+| I/O                      |     0.029 |      202 |       400 |           50.50 |
-| I/O                      |     0.023 |      202 |       400 |           50.50 |
 | Static Power             |     0.141 |          |           |                 |
-| Total                    |     0.549 |          |           |                 |
+| Total                    |     0.686 |          |           |                 |
+=======
+| Clocks                   |     0.060 |        7 |       --- |             --- |
+| Slice Logic              |     0.137 |   103629 |       --- |             --- |
+|   LUT as Logic           |     0.128 |    53158 |    133800 |           39.73 |
+|   CARRY4                 |     0.005 |     3669 |     33450 |           10.97 |
+|   Register               |     0.002 |    31000 |    267600 |           11.58 |
+|   LUT as Distributed RAM |     0.001 |      740 |     46200 |            1.60 |
+|   LUT as Shift Register  |    <0.001 |     1168 |     46200 |            2.53 |
+|   F7/F8 Muxes            |    <0.001 |     2449 |    133800 |            1.83 |
+|   Others                 |     0.000 |      333 |       --- |             --- |
+| Signals                  |     0.284 |    78815 |       --- |             --- |
+| Block RAM                |     0.027 |     29.5 |       365 |            8.08 |
+| PLL                      |     0.102 |        1 |        10 |           10.00 |
+| I/O                      |     0.027 |      202 |       400 |           50.50 |
+| Static Power             |     0.142 |          |           |                 |
+| Total                    |     0.779 |          |           |                 |
+>>>>>>> Stashed changes
 +--------------------------+-----------+----------+-----------+-----------------+
 
 
@@ -77,16 +109,21 @@ Table of Contents
 +-----------+-------------+-----------+-------------+------------+
 | Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
 +-----------+-------------+-----------+-------------+------------+
-| Vccint    |       1.000 |     0.294 |       0.262 |      0.032 |
+<<<<<<< Updated upstream
-| Vccaux    |       1.800 |     0.099 |       0.069 |      0.031 |
+| Vccint    |       1.000 |     0.423 |       0.391 |      0.032 |
-| Vcco33    |       3.300 |     0.011 |       0.006 |      0.005 |
+| Vccaux    |       1.800 |     0.101 |       0.070 |      0.031 |
+=======
+| Vccint    |       1.000 |     0.545 |       0.512 |      0.033 |
+| Vccaux    |       1.800 |     0.085 |       0.054 |      0.031 |
+>>>>>>> Stashed changes
+| Vcco33    |       3.300 |     0.013 |       0.008 |      0.005 |
 | Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
 | Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
 | Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
 | Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
 | Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
 | Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
-| Vccbram   |       1.000 |     0.003 |       0.001 |      0.001 |
+| Vccbram   |       1.000 |     0.003 |       0.002 |      0.001 |
 | MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
 | MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
 | Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
@@ -130,15 +167,26 @@ Table of Contents
 2.2 Clock Constraints
 ---------------------
 
-+-------------------+------------------------------------------+-----------------+
+<<<<<<< Updated upstream
-| Clock             | Domain                                   | Constraint (ns) |
++------------------+-----------------------------------------+-----------------+
-+-------------------+------------------------------------------+-----------------+
+| Clock            | Domain                                  | Constraint (ns) |
-| clk               | clk                                      |            20.0 |
++------------------+-----------------------------------------+-----------------+
-| clkfbout_clk_pll  | pll_clk.u_clk_pll/inst/clkfbout_clk_pll  |            20.0 |
+| clk              | clk                                     |            20.0 |
-| cpu_clk           | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll   |            30.3 |
+| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |            20.0 |
-| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll |            40.0 |
+| cpu_clk          | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll  |            30.3 |
-| sys_clk           | pll_clk.u_clk_pll/inst/sys_clk_clk_pll   |            20.0 |
+| sys_clk          | pll_clk.u_clk_pll/inst/sys_clk_clk_pll  |            20.0 |
-+-------------------+------------------------------------------+-----------------+
++------------------+-----------------------------------------+-----------------+
+=======
++------------------+------------------------------------------+-----------------+
+| Clock            | Domain                                   | Constraint (ns) |
++------------------+------------------------------------------+-----------------+
+| clk              | clk                                      |            20.0 |
+| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll  |            20.0 |
+| cpu_clk          | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll   |            30.0 |
+| mlkem_clk        | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll |            13.0 |
+| sys_clk          | pll_clk.u_clk_pll/inst/sys_clk_clk_pll   |            20.0 |
++------------------+------------------------------------------+-----------------+
+>>>>>>> Stashed changes
 
 
 3. Detailed Reports
@@ -150,31 +198,64 @@ Table of Contents
 +----------------------------+-----------+
 | Name                       | Power (W) |
 +----------------------------+-----------+
-| soc_top                    |     0.409 |
+<<<<<<< Updated upstream
-|   pll_clk.u_clk_pll        |     0.133 |
+| soc_top                    |     0.545 |
-|     inst                   |     0.133 |
+|   pll_clk.u_clk_pll        |     0.138 |
+|     inst                   |     0.138 |
+|   u_Axi_CDC                |     0.003 |
+|   u_axi_uart_controller    |     0.002 |
+|   u_cpu                    |     0.025 |
+|     addr_trans             |     0.002 |
+|       tlb_entry            |     0.002 |
+|     btb                    |     0.003 |
+|     dcache                 |     0.006 |
+|     icache                 |     0.005 |
+|     u_csr                  |     0.001 |
+|     u_mul                  |     0.004 |
+|   u_fft_mlkem_axi_slave    |     0.251 |
+|     u_fft_controller       |     0.030 |
+|       u_FFT                |     0.027 |
+|       u_out0               |     0.001 |
+|       u_out1               |     0.001 |
+|     u_mlkem_axi_slave      |     0.221 |
+|       u_mlkem              |     0.218 |
+|   u_matmul_axi_slave       |     0.081 |
+=======
+| soc_top                    |     0.637 |
+|   pll_clk.u_clk_pll        |     0.103 |
+|     inst                   |     0.103 |
 |   u_Axi_CDC                |     0.002 |
-|   u_axi_uart_controller    |     0.001 |
+|   u_axi_uart_controller    |     0.002 |
 |     uart0                  |     0.001 |
 |       regs                 |     0.001 |
 |   u_cdma_matmul_bridge     |     0.001 |
-|   u_cpu                    |     0.018 |
+|   u_confreg                |     0.001 |
+|   u_cpu                    |     0.027 |
 |     addr_trans             |     0.002 |
 |       tlb_entry            |     0.002 |
-|     btb                    |     0.002 |
+|     btb                    |     0.003 |
 |     dcache                 |     0.004 |
 |     icache                 |     0.005 |
-|     u_csr                  |     0.002 |
+|     u_csr                  |     0.001 |
-|   u_fft_mlkem_axi_slave    |     0.148 |
+|     u_mul                  |     0.008 |
-|     u_fft_controller       |     0.032 |
+|   u_fft_mlkem_axi_slave    |     0.373 |
-|       u_FFT                |     0.029 |
+|     u_fft_controller       |     0.031 |
-|     u_mlkem_axi_cdc        |     0.002 |
+|       u_FFT                |     0.028 |
-|     u_mlkem_axi_slave      |     0.115 |
+|       u_out0               |     0.001 |
-|       u_mlkem              |     0.113 |
+|       u_out1               |     0.001 |
-|   u_matmul_axi_slave       |     0.065 |
+|     u_mlkem_axi_cdc        |     0.003 |
-|   u_snix_axil_cdma_mux_8ch |     0.009 |
+|       wFifo                |     0.001 |
+|     u_mlkem_axi_slave      |     0.339 |
+|       u_mlkem              |     0.332 |
+|   u_matmul_axi_slave       |     0.077 |
+>>>>>>> Stashed changes
+|     mult_inst[0].u_mult    |     0.003 |
+|     mult_inst[1].u_mult    |     0.002 |
+|     mult_inst[2].u_mult    |     0.002 |
+|     mult_inst[3].u_mult    |     0.002 |
+|   u_snix_axil_cdma_mux_8ch |     0.008 |
 |     u_core_engine          |     0.004 |
-|       axis_fifo_u0         |     0.003 |
+|       axis_fifo_u0         |     0.002 |
 +----------------------------+-----------+
 
 

fpga/vivado_reports_nodsp/route_status.rpt

@@ -1,12 +1,21 @@
 Design Route Status
                                                :      # nets :
    ------------------------------------------- : ----------- :
-   # of logical nets.......................... :      128919 :
+<<<<<<< Updated upstream
-       # of nets not needing routing.......... :       43824 :
+   # of logical nets.......................... :      144034 :
-           # of internally routed nets........ :       43359 :
+       # of nets not needing routing.......... :       50823 :
+           # of internally routed nets........ :       50442 :
+           # of nets with no loads............ :         381 :
+       # of routable nets..................... :       93211 :
+           # of fully routed nets............. :       93211 :
+=======
+   # of logical nets.......................... :      114880 :
+       # of nets not needing routing.......... :       36054 :
+           # of internally routed nets........ :       35589 :
            # of nets with no loads............ :         465 :
-       # of routable nets..................... :       85095 :
+       # of routable nets..................... :       78826 :
-           # of fully routed nets............. :       85095 :
+           # of fully routed nets............. :       78826 :
+>>>>>>> Stashed changes
        # of nets with routing errors.......... :           0 :
    ------------------------------------------- : ----------- :
 

fpga/vivado_reports_nodsp/utilization.rpt

@@ -1,13 +1,17 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:05 2026
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:47 2026
+=======
+| Date         : Sat Jul 11 09:20:51 2026
+>>>>>>> Stashed changes
 | Host         : fedora running 64-bit unknown
-| Command      : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt
+| Command      : report_utilization -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization.rpt
 | Design       : soc_top
 | Device       : 7a200tfbg676-1
 | Design State : Routed
-------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------------------------------------
 
 Utilization Design Information
 
@@ -31,16 +35,29 @@ Table of Contents
 +----------------------------+-------+-------+-----------+-------+
 |          Site Type         |  Used | Fixed | Available | Util% |
 +----------------------------+-------+-------+-----------+-------+
-| Slice LUTs                 | 60995 |     0 |    133800 | 45.59 |
+<<<<<<< Updated upstream
-|   LUT as Logic             | 59140 |     0 |    133800 | 44.20 |
+| Slice LUTs                 | 71196 |     0 |    133800 | 53.21 |
-|   LUT as Memory            |  1855 |     0 |     46200 |  4.02 |
+|   LUT as Logic             | 69453 |     0 |    133800 | 51.91 |
-|     LUT as Distributed RAM |   740 |     0 |           |       |
+|   LUT as Memory            |  1743 |     0 |     46200 |  3.77 |
+|     LUT as Distributed RAM |   628 |     0 |           |       |
 |     LUT as Shift Register  |  1115 |     0 |           |       |
-| Slice Registers            | 39931 |     0 |    267600 | 14.92 |
+| Slice Registers            | 39690 |     0 |    267600 | 14.83 |
-|   Register as Flip Flop    | 39931 |     0 |    267600 | 14.92 |
+|   Register as Flip Flop    | 39690 |     0 |    267600 | 14.83 |
 |   Register as Latch        |     0 |     0 |    267600 |  0.00 |
-| F7 Muxes                   |  4480 |     0 |     66900 |  6.70 |
+| F7 Muxes                   |  4565 |     0 |     66900 |  6.82 |
-| F8 Muxes                   |  1556 |     0 |     33450 |  4.65 |
+| F8 Muxes                   |  1520 |     0 |     33450 |  4.54 |
+=======
+| Slice LUTs                 | 55066 |     0 |    133800 | 41.16 |
+|   LUT as Logic             | 53158 |     0 |    133800 | 39.73 |
+|   LUT as Memory            |  1908 |     0 |     46200 |  4.13 |
+|     LUT as Distributed RAM |   740 |     0 |           |       |
+|     LUT as Shift Register  |  1168 |     0 |           |       |
+| Slice Registers            | 31000 |     0 |    267600 | 11.58 |
+|   Register as Flip Flop    | 31000 |     0 |    267600 | 11.58 |
+|   Register as Latch        |     0 |     0 |    267600 |  0.00 |
+| F7 Muxes                   |  2130 |     0 |     66900 |  3.18 |
+| F8 Muxes                   |   319 |     0 |     33450 |  0.95 |
+>>>>>>> Stashed changes
 +----------------------------+-------+-------+-----------+-------+
 
 
@@ -57,9 +74,15 @@ Table of Contents
 | 0     |            _ |       Reset |            - |
 | 0     |          Yes |           - |            - |
 | 24    |          Yes |           - |          Set |
-| 26637 |          Yes |           - |        Reset |
+<<<<<<< Updated upstream
+| 26562 |          Yes |           - |        Reset |
 | 139   |          Yes |         Set |            - |
-| 13131 |          Yes |       Reset |            - |
+| 12965 |          Yes |       Reset |            - |
+=======
+| 17683 |          Yes |           - |        Reset |
+| 126   |          Yes |         Set |            - |
+| 13167 |          Yes |       Reset |            - |
+>>>>>>> Stashed changes
 +-------+--------------+-------------+--------------+
 
 
@@ -69,28 +92,53 @@ Table of Contents
 +--------------------------------------------+-------+-------+-----------+-------+
 |                  Site Type                 |  Used | Fixed | Available | Util% |
 +--------------------------------------------+-------+-------+-----------+-------+
-| Slice                                      | 20066 |     0 |     33450 | 59.99 |
+<<<<<<< Updated upstream
-|   SLICEL                                   | 13210 |     0 |           |       |
+| Slice                                      | 21289 |     0 |     33450 | 63.64 |
-|   SLICEM                                   |  6856 |     0 |           |       |
+|   SLICEL                                   | 13965 |     0 |           |       |
-| LUT as Logic                               | 59140 |     0 |    133800 | 44.20 |
+|   SLICEM                                   |  7324 |     0 |           |       |
+| LUT as Logic                               | 69453 |     0 |    133800 | 51.91 |
 |   using O5 output only                     |     2 |       |           |       |
-|   using O6 output only                     | 49931 |       |           |       |
+|   using O6 output only                     | 57661 |       |           |       |
-|   using O5 and O6                          |  9207 |       |           |       |
+|   using O5 and O6                          | 11790 |       |           |       |
-| LUT as Memory                              |  1855 |     0 |     46200 |  4.02 |
+| LUT as Memory                              |  1743 |     0 |     46200 |  3.77 |
-|   LUT as Distributed RAM                   |   740 |     0 |           |       |
+|   LUT as Distributed RAM                   |   628 |     0 |           |       |
 |     using O5 output only                   |     0 |       |           |       |
 |     using O6 output only                   |    60 |       |           |       |
-|     using O5 and O6                        |   680 |       |           |       |
+|     using O5 and O6                        |   568 |       |           |       |
 |   LUT as Shift Register                    |  1115 |     0 |           |       |
 |     using O5 output only                   |    47 |       |           |       |
 |     using O6 output only                   |  1008 |       |           |       |
 |     using O5 and O6                        |    60 |       |           |       |
-| Slice Registers                            | 39931 |     0 |    267600 | 14.92 |
+| Slice Registers                            | 39690 |     0 |    267600 | 14.83 |
-|   Register driven from within the Slice    | 20433 |       |           |       |
+|   Register driven from within the Slice    | 24917 |       |           |       |
-|   Register driven from outside the Slice   | 19498 |       |           |       |
+|   Register driven from outside the Slice   | 14773 |       |           |       |
-|     LUT in front of the register is unused | 10788 |       |           |       |
+|     LUT in front of the register is unused |  6243 |       |           |       |
-|     LUT in front of the register is used   |  8710 |       |           |       |
+|     LUT in front of the register is used   |  8530 |       |           |       |
-| Unique Control Sets                        |  1304 |       |     33450 |  3.90 |
+| Unique Control Sets                        |  1278 |       |     33450 |  3.82 |
+=======
+| Slice                                      | 17126 |     0 |     33450 | 51.20 |
+|   SLICEL                                   | 11119 |     0 |           |       |
+|   SLICEM                                   |  6007 |     0 |           |       |
+| LUT as Logic                               | 53158 |     0 |    133800 | 39.73 |
+|   using O5 output only                     |     5 |       |           |       |
+|   using O6 output only                     | 42769 |       |           |       |
+|   using O5 and O6                          | 10384 |       |           |       |
+| LUT as Memory                              |  1908 |     0 |     46200 |  4.13 |
+|   LUT as Distributed RAM                   |   740 |     0 |           |       |
+|     using O5 output only                   |     0 |       |           |       |
+|     using O6 output only                   |    60 |       |           |       |
+|     using O5 and O6                        |   680 |       |           |       |
+|   LUT as Shift Register                    |  1168 |     0 |           |       |
+|     using O5 output only                   |   123 |       |           |       |
+|     using O6 output only                   |   997 |       |           |       |
+|     using O5 and O6                        |    48 |       |           |       |
+| Slice Registers                            | 31000 |     0 |    267600 | 11.58 |
+|   Register driven from within the Slice    | 16668 |       |           |       |
+|   Register driven from outside the Slice   | 14332 |       |           |       |
+|     LUT in front of the register is unused |  5924 |       |           |       |
+|     LUT in front of the register is used   |  8408 |       |           |       |
+| Unique Control Sets                        |   930 |       |     33450 |  2.78 |
+>>>>>>> Stashed changes
 +--------------------------------------------+-------+-------+-----------+-------+
 * Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
 
@@ -101,11 +149,19 @@ Table of Contents
 +-------------------+------+-------+-----------+-------+
 |     Site Type     | Used | Fixed | Available | Util% |
 +-------------------+------+-------+-----------+-------+
-| Block RAM Tile    | 23.5 |     0 |       365 |  6.44 |
+<<<<<<< Updated upstream
-|   RAMB36/FIFO*    |    8 |     0 |       365 |  2.19 |
+| Block RAM Tile    | 25.5 |     0 |       365 |  6.99 |
-|     RAMB36E1 only |    8 |       |           |       |
+|   RAMB36/FIFO*    |   10 |     0 |       365 |  2.74 |
+|     RAMB36E1 only |   10 |       |           |       |
 |   RAMB18          |   31 |     0 |       730 |  4.25 |
 |     RAMB18E1 only |   31 |       |           |       |
+=======
+| Block RAM Tile    | 29.5 |     0 |       365 |  8.08 |
+|   RAMB36/FIFO*    |   10 |     0 |       365 |  2.74 |
+|     RAMB36E1 only |   10 |       |           |       |
+|   RAMB18          |   39 |     0 |       730 |  5.34 |
+|     RAMB18E1 only |   39 |       |           |       |
+>>>>>>> Stashed changes
 +-------------------+------+-------+-----------+-------+
 * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
 
@@ -113,12 +169,11 @@ Table of Contents
 4. DSP
 ------
 
-+----------------+------+-------+-----------+-------+
++-----------+------+-------+-----------+-------+
-|    Site Type   | Used | Fixed | Available | Util% |
+| Site Type | Used | Fixed | Available | Util% |
-+----------------+------+-------+-----------+-------+
++-----------+------+-------+-----------+-------+
-| DSPs           |   16 |     0 |       740 |  2.16 |
+| DSPs      |    0 |     0 |       740 |  0.00 |
-|   DSP48E1 only |   16 |       |           |       |
++-----------+------+-------+-----------+-------+
-+----------------+------+-------+-----------+-------+
 
 
 5. IO and GT Specific
@@ -154,7 +209,7 @@ Table of Contents
 +------------+------+-------+-----------+-------+
 |  Site Type | Used | Fixed | Available | Util% |
 +------------+------+-------+-----------+-------+
-| BUFGCTRL   |    4 |     0 |        32 | 12.50 |
+| BUFGCTRL   |    3 |     0 |        32 |  9.38 |
 | BUFIO      |    0 |     0 |        40 |  0.00 |
 | MMCME2_ADV |    0 |     0 |        10 |  0.00 |
 | PLLE2_ADV  |    1 |     0 |        10 | 10.00 |
@@ -188,31 +243,53 @@ Table of Contents
 +-----------+-------+---------------------+
 |  Ref Name |  Used | Functional Category |
 +-----------+-------+---------------------+
-| LUT6      | 35413 |                 LUT |
+<<<<<<< Updated upstream
-| FDCE      | 26637 |        Flop & Latch |
+| LUT6      | 37981 |                 LUT |
-| FDRE      | 13131 |        Flop & Latch |
+| FDCE      | 26562 |        Flop & Latch |
-| LUT3      |  9384 |                 LUT |
+| FDRE      | 12965 |        Flop & Latch |
-| LUT5      |  8477 |                 LUT |
+| LUT5      | 12781 |                 LUT |
-| LUT4      |  7294 |                 LUT |
+| LUT4      | 10316 |                 LUT |
-| LUT2      |  6978 |                 LUT |
+| LUT3      | 10135 |                 LUT |
-| MUXF7     |  4480 |               MuxFx |
+| LUT2      |  9228 |                 LUT |
-| CARRY4    |  2859 |          CarryLogic |
+| MUXF7     |  4565 |               MuxFx |
-| MUXF8     |  1556 |               MuxFx |
+| CARRY4    |  3546 |          CarryLogic |
-| RAMD32    |  1060 |  Distributed Memory |
+| MUXF8     |  1520 |               MuxFx |
 | SRLC32E   |   992 |  Distributed Memory |
-| LUT1      |   801 |                 LUT |
+| RAMD32    |   892 |  Distributed Memory |
-| RAMS32    |   328 |  Distributed Memory |
+| LUT1      |   802 |                 LUT |
+| RAMS32    |   272 |  Distributed Memory |
 | SRL16E    |   183 |  Distributed Memory |
 | FDSE      |   139 |        Flop & Latch |
+=======
+| LUT6      | 26800 |                 LUT |
+| FDCE      | 17683 |        Flop & Latch |
+| FDRE      | 13167 |        Flop & Latch |
+| LUT3      | 10370 |                 LUT |
+| LUT4      |  8684 |                 LUT |
+| LUT2      |  8543 |                 LUT |
+| LUT5      |  8274 |                 LUT |
+| CARRY4    |  3669 |          CarryLogic |
+| MUXF7     |  2130 |               MuxFx |
+| RAMD32    |  1060 |  Distributed Memory |
+| SRLC32E   |   992 |  Distributed Memory |
+| LUT1      |   871 |                 LUT |
+| RAMS32    |   328 |  Distributed Memory |
+| MUXF8     |   319 |               MuxFx |
+| SRL16E    |   224 |  Distributed Memory |
+| FDSE      |   126 |        Flop & Latch |
+>>>>>>> Stashed changes
 | IBUF      |   104 |                  IO |
 | OBUF      |    98 |                  IO |
 | OBUFT     |    66 |                  IO |
+| RAMB18E1  |    39 |        Block Memory |
 | RAMD64E   |    32 |  Distributed Memory |
-| RAMB18E1  |    31 |        Block Memory |
 | FDPE      |    24 |        Flop & Latch |
-| DSP48E1   |    16 |    Block Arithmetic |
+| RAMB36E1  |    10 |        Block Memory |
-| RAMB36E1  |     8 |        Block Memory |
+<<<<<<< Updated upstream
+| BUFG      |     3 |               Clock |
+=======
 | BUFG      |     4 |               Clock |
+>>>>>>> Stashed changes
 | PLLE2_ADV |     1 |               Clock |
 +-----------+-------+---------------------+
 

fpga/vivado_reports_nodsp/utilization_hier.rpt

@@ -1,13 +1,13 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:06 2026
+| Date         : Sat Jul 11 09:20:51 2026
 | Host         : fedora running 64-bit unknown
-| Command      : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt
+| Command      : report_utilization -hierarchical -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization_hier.rpt
 | Design       : soc_top
 | Device       : 7a200tfbg676-1
 | Design State : Routed
--------------------------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------
 
 Utilization Design Information
 
@@ -21,255 +21,269 @@ Table of Contents
 +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
 |                 Instance                 |            Module            | Total LUTs | Logic LUTs | LUTRAMs | SRLs |  FFs  | RAMB36 | RAMB18 | DSP48 Blocks |
 +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
-| soc_top                                  |                        (top) |      60995 |      59140 |     740 | 1115 | 39931 |      8 |     31 |           16 |
+| soc_top                                  |                        (top) |      55066 |      53158 |     740 | 1168 | 31000 |     10 |     39 |            0 |
-|   (soc_top)                              |                        (top) |        878 |        822 |      56 |    0 |     4 |      0 |      0 |            0 |
+|   (soc_top)                              |                        (top) |        927 |        919 |       8 |    0 |     4 |      0 |      0 |            0 |
 |   pll_clk.u_clk_pll                      |                      clk_pll |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
-|     inst                                 |     clk_pll__clk_pll_clk_wiz |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|     inst                                 |      clk_pll_clk_pll_clk_wiz |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
 |   pll_clk.u_rst_cpu                      |                     rst_sync |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
 |   pll_clk.u_rst_mlkem                    |                   rst_sync_0 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
 |   pll_clk.u_rst_sys                      |                   rst_sync_1 |          2 |          2 |       0 |    0 |     2 |      0 |      0 |            0 |
-|   u_AxiCrossbar_2x8                      |              AxiCrossbar_2x8 |        459 |        459 |       0 |    0 |   151 |      0 |      0 |            0 |
+|   u_AxiCrossbar_2x8                      |              AxiCrossbar_2x8 |        368 |        368 |       0 |    0 |   151 |      0 |      0 |            0 |
-|     (u_AxiCrossbar_2x8)                  |              AxiCrossbar_2x8 |          6 |          6 |       0 |    0 |    24 |      0 |      0 |            0 |
+|     (u_AxiCrossbar_2x8)                  |              AxiCrossbar_2x8 |          8 |          8 |       0 |    0 |    24 |      0 |      0 |            0 |
-|     axi4ReadOnlyArbiter_4                |          Axi4ReadOnlyArbiter |         18 |         18 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_4                |          Axi4ReadOnlyArbiter |         14 |         14 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_82 |         18 |         18 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_92 |         14 |         14 |       0 |    0 |     3 |      0 |      0 |            0 |
-|     axi4ReadOnlyArbiter_5                |       Axi4ReadOnlyArbiter_65 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_5                |       Axi4ReadOnlyArbiter_75 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_81 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_91 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
-|     axi4ReadOnlyArbiter_6                |       Axi4ReadOnlyArbiter_66 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_6                |       Axi4ReadOnlyArbiter_76 |         17 |         17 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_80 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_90 |         17 |         17 |       0 |    0 |     3 |      0 |      0 |            0 |
-|     axi4ReadOnlyArbiter_7                |       Axi4ReadOnlyArbiter_67 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_7                |       Axi4ReadOnlyArbiter_77 |         13 |         13 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_79 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_89 |         13 |         13 |       0 |    0 |     3 |      0 |      0 |            0 |
-|     axi4WriteOnlyArbiter_4               |         Axi4WriteOnlyArbiter |         33 |         33 |       0 |    0 |    11 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_4               |         Axi4WriteOnlyArbiter |         32 |         32 |       0 |    0 |    11 |      0 |      0 |            0 |
 |       (axi4WriteOnlyArbiter_4)           |         Axi4WriteOnlyArbiter |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_76 |         27 |         27 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_86 |         26 |         26 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_77 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_87 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         fifo                             |              StreamFifo_3_78 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_88 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
 |     axi4WriteOnlyArbiter_5               |       Axi4WriteOnlyArbiter_1 |         15 |         15 |       0 |    0 |     9 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_73 |          7 |          7 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_83 |          9 |          9 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_74 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_84 |          6 |          6 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         fifo                             |              StreamFifo_3_75 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_85 |          6 |          6 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     axi4WriteOnlyArbiter_6               |       Axi4WriteOnlyArbiter_2 |         29 |         29 |       0 |    0 |    11 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_6               |       Axi4WriteOnlyArbiter_2 |         33 |         33 |       0 |    0 |    11 |      0 |      0 |            0 |
 |       (axi4WriteOnlyArbiter_6)           |       Axi4WriteOnlyArbiter_2 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_70 |         20 |         20 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_80 |         24 |         24 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_71 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_81 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         fifo                             |              StreamFifo_3_72 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_82 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     axi4WriteOnlyArbiter_7               |       Axi4WriteOnlyArbiter_3 |         23 |         23 |       0 |    0 |    11 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_7               |       Axi4WriteOnlyArbiter_3 |         29 |         29 |       0 |    0 |    11 |      0 |      0 |            0 |
 |       (axi4WriteOnlyArbiter_7)           |       Axi4WriteOnlyArbiter_3 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       cmdArbiter                         |              StreamArbiter_7 |         15 |         15 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |              StreamArbiter_7 |         21 |         21 |       0 |    0 |     3 |      0 |      0 |            0 |
 |       cmdRouteFork_translated_fifo       |       StreamFifoLowLatency_3 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
 |         fifo                             |                 StreamFifo_3 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     axiIn_0_readOnly_decoder             |          Axi4ReadOnlyDecoder |         96 |         96 |       0 |    0 |    25 |      0 |      0 |            0 |
+|     axiIn_0_readOnly_decoder             |          Axi4ReadOnlyDecoder |         90 |         90 |       0 |    0 |    25 |      0 |      0 |            0 |
-|       (axiIn_0_readOnly_decoder)         |          Axi4ReadOnlyDecoder |         75 |         75 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       (axiIn_0_readOnly_decoder)         |          Axi4ReadOnlyDecoder |         74 |         74 |       0 |    0 |    12 |      0 |      0 |            0 |
-|       errorSlave                         |  Axi4ReadOnlyErrorSlave_1_69 |         21 |         21 |       0 |    0 |    13 |      0 |      0 |            0 |
+|       errorSlave                         |  Axi4ReadOnlyErrorSlave_1_79 |         16 |         16 |       0 |    0 |    13 |      0 |      0 |            0 |
-|     axiIn_0_writeOnly_decoder            |         Axi4WriteOnlyDecoder |         40 |         40 |       0 |    0 |    18 |      0 |      0 |            0 |
+|     axiIn_0_writeOnly_decoder            |         Axi4WriteOnlyDecoder |         36 |         36 |       0 |    0 |    18 |      0 |      0 |            0 |
-|       (axiIn_0_writeOnly_decoder)        |         Axi4WriteOnlyDecoder |         20 |         20 |       0 |    0 |    16 |      0 |      0 |            0 |
+|       (axiIn_0_writeOnly_decoder)        |         Axi4WriteOnlyDecoder |         16 |         16 |       0 |    0 |    16 |      0 |      0 |            0 |
-|       errorSlave                         | Axi4WriteOnlyErrorSlave_1_68 |         21 |         21 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       errorSlave                         | Axi4WriteOnlyErrorSlave_1_78 |         20 |         20 |       0 |    0 |     2 |      0 |      0 |            0 |
-|     axiIn_1_readOnly_decoder             |        Axi4ReadOnlyDecoder_1 |        133 |        133 |       0 |    0 |    17 |      0 |      0 |            0 |
+|     axiIn_1_readOnly_decoder             |        Axi4ReadOnlyDecoder_1 |         52 |         52 |       0 |    0 |    17 |      0 |      0 |            0 |
-|       (axiIn_1_readOnly_decoder)         |        Axi4ReadOnlyDecoder_1 |        118 |        118 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       (axiIn_1_readOnly_decoder)         |        Axi4ReadOnlyDecoder_1 |         36 |         36 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       errorSlave                         |     Axi4ReadOnlyErrorSlave_1 |         15 |         15 |       0 |    0 |     9 |      0 |      0 |            0 |
+|       errorSlave                         |     Axi4ReadOnlyErrorSlave_1 |         16 |         16 |       0 |    0 |     9 |      0 |      0 |            0 |
-|     axiIn_1_writeOnly_decoder            |       Axi4WriteOnlyDecoder_1 |         30 |         30 |       0 |    0 |    14 |      0 |      0 |            0 |
+|     axiIn_1_writeOnly_decoder            |       Axi4WriteOnlyDecoder_1 |         23 |         23 |       0 |    0 |    14 |      0 |      0 |            0 |
-|       (axiIn_1_writeOnly_decoder)        |       Axi4WriteOnlyDecoder_1 |         18 |         18 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       (axiIn_1_writeOnly_decoder)        |       Axi4WriteOnlyDecoder_1 |         15 |         15 |       0 |    0 |    12 |      0 |      0 |            0 |
-|       errorSlave                         |    Axi4WriteOnlyErrorSlave_1 |         12 |         12 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       errorSlave                         |    Axi4WriteOnlyErrorSlave_1 |          8 |          8 |       0 |    0 |     2 |      0 |      0 |            0 |
-|   u_Axi_CDC                              |                      Axi_CDC |        410 |        282 |     128 |    0 |   317 |      0 |      0 |            0 |
+|   u_Axi_CDC                              |                      Axi_CDC |        427 |        299 |     128 |    0 |   317 |      0 |      0 |            0 |
-|     arFifo                               |            StreamFifoCC_3_48 |        181 |        145 |      36 |    0 |    77 |      0 |      0 |            0 |
+|     arFifo                               |            StreamFifoCC_3_58 |        192 |        156 |      36 |    0 |    77 |      0 |      0 |            0 |
-|       (arFifo)                           |            StreamFifoCC_3_48 |        176 |        140 |      36 |    0 |    65 |      0 |      0 |            0 |
+|       (arFifo)                           |            StreamFifoCC_3_58 |        186 |        150 |      36 |    0 |    65 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                BufferCC_9_63 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_9_73 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |               BufferCC_11_64 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |               BufferCC_11_74 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     awFifo                               |              StreamFifoCC_49 |        103 |         67 |      36 |    0 |    79 |      0 |      0 |            0 |
+|     awFifo                               |              StreamFifoCC_59 |        110 |         74 |      36 |    0 |    79 |      0 |      0 |            0 |
-|       (awFifo)                           |              StreamFifoCC_49 |         99 |         63 |      36 |    0 |    65 |      0 |      0 |            0 |
+|       (awFifo)                           |              StreamFifoCC_59 |        103 |         67 |      36 |    0 |    65 |      0 |      0 |            0 |
-|       bufferCC_12                        |               BufferCC_10_60 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       bufferCC_12                        |               BufferCC_10_70 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                BufferCC_9_61 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_9_71 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |               BufferCC_11_62 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |               BufferCC_11_72 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     bFifo                                |            StreamFifoCC_2_50 |         15 |         15 |       0 |    0 |    26 |      0 |      0 |            0 |
+|     bFifo                                |            StreamFifoCC_2_60 |         14 |         14 |       0 |    0 |    26 |      0 |      0 |            0 |
-|       (bFifo)                            |            StreamFifoCC_2_50 |          8 |          8 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       (bFifo)                            |            StreamFifoCC_2_60 |          7 |          7 |       0 |    0 |    12 |      0 |      0 |            0 |
-|       bufferCC_12                        |                BufferCC_5_57 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       bufferCC_12                        |                BufferCC_5_67 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                BufferCC_4_58 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_4_68 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |                BufferCC_6_59 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_6_69 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     rFifo                                |            StreamFifoCC_4_51 |         45 |         17 |      28 |    0 |    66 |      0 |      0 |            0 |
+|     rFifo                                |            StreamFifoCC_4_61 |         45 |         17 |      28 |    0 |    66 |      0 |      0 |            0 |
-|       (rFifo)                            |            StreamFifoCC_4_51 |         41 |         13 |      28 |    0 |    50 |      0 |      0 |            0 |
+|       (rFifo)                            |            StreamFifoCC_4_61 |         41 |         13 |      28 |    0 |    50 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                  BufferCC_55 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                  BufferCC_65 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |                BufferCC_1_56 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_1_66 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
-|     wFifo                                |            StreamFifoCC_1_52 |         66 |         38 |      28 |    0 |    69 |      0 |      0 |            0 |
+|     wFifo                                |            StreamFifoCC_1_62 |         66 |         38 |      28 |    0 |    69 |      0 |      0 |            0 |
-|       (wFifo)                            |            StreamFifoCC_1_52 |         62 |         34 |      28 |    0 |    53 |      0 |      0 |            0 |
+|       (wFifo)                            |            StreamFifoCC_1_62 |         62 |         34 |      28 |    0 |    53 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                BufferCC_7_53 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_7_63 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |                BufferCC_8_54 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_8_64 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
-|   u_axi_axil_adapter                     |             axi_axil_adapter |       1073 |       1073 |       0 |    0 |   173 |      0 |      0 |            0 |
+|   u_axi_axil_adapter                     |             axi_axil_adapter |       1245 |       1245 |       0 |    0 |   161 |      0 |      0 |            0 |
-|     axi_axil_adapter_rd_inst             |          axi_axil_adapter_rd |        498 |        498 |       0 |    0 |    85 |      0 |      0 |            0 |
+|     axi_axil_adapter_rd_inst             |          axi_axil_adapter_rd |        640 |        640 |       0 |    0 |    81 |      0 |      0 |            0 |
-|     axi_axil_adapter_wr_inst             |          axi_axil_adapter_wr |        575 |        575 |       0 |    0 |    88 |      0 |      0 |            0 |
+|     axi_axil_adapter_wr_inst             |          axi_axil_adapter_wr |        605 |        605 |       0 |    0 |    80 |      0 |      0 |            0 |
-|   u_axi_dvi                              |                      axi_dvi |        283 |        283 |       0 |    0 |   211 |      0 |      0 |            0 |
+|   u_axi_dvi                              |                      axi_dvi |        284 |        284 |       0 |    0 |   211 |      0 |      0 |            0 |
-|   u_axi_ram                              |     axi_wrap_ram_sp_external |        350 |        350 |       0 |    0 |    78 |      0 |      0 |            0 |
+|   u_axi_ram                              |     axi_wrap_ram_sp_external |        356 |        356 |       0 |    0 |    78 |      0 |      0 |            0 |
-|     u_axi_sram_sp                        |         axi2sram_sp_external |        350 |        350 |       0 |    0 |    78 |      0 |      0 |            0 |
+|     u_axi_sram_sp                        |         axi2sram_sp_external |        356 |        356 |       0 |    0 |    78 |      0 |      0 |            0 |
-|   u_axi_uart_controller                  |          axi_uart_controller |        683 |        667 |      16 |    0 |   457 |      0 |      0 |            0 |
+|   u_axi_uart_controller                  |          axi_uart_controller |        684 |        668 |      16 |    0 |   457 |      0 |      0 |            0 |
-|     AA_axi2apb_bridge_cpu                |               axi2apb_bridge |        251 |        251 |       0 |    0 |   120 |      0 |      0 |            0 |
+|     AA_axi2apb_bridge_cpu                |               axi2apb_bridge |        252 |        252 |       0 |    0 |   120 |      0 |      0 |            0 |
 |     uart0                                |                     UART_TOP |        432 |        416 |      16 |    0 |   337 |      0 |      0 |            0 |
 |       regs                               |                    uart_regs |        432 |        416 |      16 |    0 |   337 |      0 |      0 |            0 |
-|         (regs)                           |                    uart_regs |        119 |        119 |       0 |    0 |   155 |      0 |      0 |            0 |
+|         (regs)                           |                    uart_regs |        118 |        118 |       0 |    0 |   155 |      0 |      0 |            0 |
 |         i_uart_sync_flops                |              uart_sync_flops |          3 |          3 |       0 |    0 |     2 |      0 |      0 |            0 |
 |         receiver                         |                uart_receiver |        229 |        221 |       8 |    0 |   124 |      0 |      0 |            0 |
 |           (receiver)                     |                uart_receiver |         68 |         68 |       0 |    0 |    54 |      0 |      0 |            0 |
 |           fifo_rx                        |                   uart_rfifo |        161 |        153 |       8 |    0 |    70 |      0 |      0 |            0 |
 |             (fifo_rx)                    |                   uart_rfifo |        143 |        143 |       0 |    0 |    62 |      0 |      0 |            0 |
-|             rfifo                        |                   raminfr_47 |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
+|             rfifo                        |                   raminfr_57 |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
 |         transmitter                      |             uart_transmitter |         83 |         75 |       8 |    0 |    56 |      0 |      0 |            0 |
 |           (transmitter)                  |             uart_transmitter |         41 |         41 |       0 |    0 |    35 |      0 |      0 |            0 |
 |           fifo_tx                        |                   uart_tfifo |         43 |         35 |       8 |    0 |    21 |      0 |      0 |            0 |
 |             (fifo_tx)                    |                   uart_tfifo |         24 |         24 |       0 |    0 |    13 |      0 |      0 |            0 |
 |             tfifo                        |                      raminfr |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
-|   u_cdma_matmul_bridge                   |           cdma_matmul_bridge |        251 |        251 |       0 |    0 |   578 |      0 |      0 |            0 |
+|   u_cdma_matmul_bridge                   |           cdma_matmul_bridge |        248 |        248 |       0 |    0 |   578 |      0 |      0 |            0 |
 |   u_confreg                              |                      confreg |        390 |        390 |       0 |    0 |   476 |      0 |      0 |            0 |
 |     (u_confreg)                          |                      confreg |        230 |        230 |       0 |    0 |   399 |      0 |      0 |            0 |
 |     u_digitaltube_controller             |       digitaltube_controller |         16 |         16 |       0 |    0 |    24 |      0 |      0 |            0 |
 |     u_int_ctrl                           |                     int_ctrl |        144 |        144 |       0 |    0 |    53 |      0 |      0 |            0 |
-|   u_cpu                                  |                     core_top |       8551 |       8299 |     252 |    0 |  5591 |      0 |     20 |            0 |
+|   u_cpu                                  |                     core_top |       8584 |       8284 |     300 |    0 |  5591 |      0 |     20 |            0 |
-|     (u_cpu)                              |                     core_top |        519 |        519 |       0 |    0 |     1 |      0 |      0 |            0 |
+|     (u_cpu)                              |                     core_top |        561 |        513 |      48 |    0 |     1 |      0 |      0 |            0 |
-|     addr_trans                           |                   addr_trans |       2247 |       2107 |     140 |    0 |  1244 |      0 |      0 |            0 |
+|     addr_trans                           |                   addr_trans |       2240 |       2100 |     140 |    0 |  1244 |      0 |      0 |            0 |
 |       (addr_trans)                       |                   addr_trans |          0 |          0 |       0 |    0 |    40 |      0 |      0 |            0 |
-|       tlb_entry                          |                    tlb_entry |       2247 |       2107 |     140 |    0 |  1204 |      0 |      0 |            0 |
+|       tlb_entry                          |                    tlb_entry |       2240 |       2100 |     140 |    0 |  1204 |      0 |      0 |            0 |
-|     axi_bridge                           |                   axi_bridge |         40 |         40 |       0 |    0 |   214 |      0 |      0 |            0 |
+|     axi_bridge                           |                   axi_bridge |         39 |         39 |       0 |    0 |   214 |      0 |      0 |            0 |
-|     btb                                  |                          btb |       1046 |        966 |      80 |    0 |  1611 |      0 |      0 |            0 |
+|     btb                                  |                          btb |       1041 |        961 |      80 |    0 |  1611 |      0 |      0 |            0 |
-|       (btb)                              |                          btb |       1044 |        964 |      80 |    0 |  1611 |      0 |      0 |            0 |
+|       (btb)                              |                          btb |       1039 |        959 |      80 |    0 |  1611 |      0 |      0 |            0 |
 |       dec_btb_add_entry                  |                 decoder_5_32 |          3 |          3 |       0 |    0 |     0 |      0 |      0 |            0 |
-|     dcache                               |                       dcache |        552 |        520 |      32 |    0 |   146 |      0 |     10 |            0 |
+|     dcache                               |                       dcache |        551 |        519 |      32 |    0 |   146 |      0 |     10 |            0 |
 |       (dcache)                           |                       dcache |         87 |         55 |      32 |    0 |   138 |      0 |      0 |            0 |
-|       data_ram_way[0].data_ram_bank[0].u |            data_bank_sram_36 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[0].u |            data_bank_sram_46 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_37 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_47 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_38 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_48 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_39 |         51 |         51 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_49 |         51 |         51 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_40 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_50 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_41 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_51 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_42 |         81 |         81 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_52 |         81 |         81 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_43 |         54 |         54 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_53 |         54 |         54 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       lfsr                               |                      lfsr_44 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       lfsr                               |                      lfsr_54 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       tagv_ram_way[0].u                  |                 tagv_sram_45 |         62 |         62 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       tagv_ram_way[0].u                  |                 tagv_sram_55 |         62 |         62 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       tagv_ram_way[1].u                  |                 tagv_sram_46 |         41 |         41 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       tagv_ram_way[1].u                  |                 tagv_sram_56 |         42 |         42 |       0 |    0 |     0 |      0 |      1 |            0 |
-|     exe_stage                            |                    exe_stage |        663 |        663 |       0 |    0 |   233 |      0 |      0 |            0 |
+|     exe_stage                            |                    exe_stage |        666 |        666 |       0 |    0 |   233 |      0 |      0 |            0 |
-|       (exe_stage)                        |                    exe_stage |        632 |        632 |       0 |    0 |   233 |      0 |      0 |            0 |
+|       (exe_stage)                        |                    exe_stage |        635 |        635 |       0 |    0 |   233 |      0 |      0 |            0 |
 |       u_alu                              |                          alu |         33 |         33 |       0 |    0 |     0 |      0 |      0 |            0 |
-|     icache                               |                       icache |        235 |        235 |       0 |    0 |    55 |      0 |     10 |            0 |
+|     icache                               |                       icache |        233 |        233 |       0 |    0 |    55 |      0 |     10 |            0 |
 |       (icache)                           |                       icache |         12 |         12 |       0 |    0 |    47 |      0 |      0 |            0 |
 |       data_ram_way[0].data_ram_bank[0].u |               data_bank_sram |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_28 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_38 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_29 |         67 |         67 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_39 |         67 |         67 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_30 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_40 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_31 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_41 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_32 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_42 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_33 |         35 |         35 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_43 |         35 |         35 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_34 |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_44 |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
 |       lfsr                               |                         lfsr |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
 |       tagv_ram_way[0].u                  |                    tagv_sram |         15 |         15 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       tagv_ram_way[1].u                  |                 tagv_sram_35 |         87 |         87 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       tagv_ram_way[1].u                  |                 tagv_sram_45 |         88 |         88 |       0 |    0 |     0 |      0 |      1 |            0 |
 |     id_stage                             |                     id_stage |       1054 |       1054 |       0 |    0 |   108 |      0 |      0 |            0 |
-|     if_stage                             |                     if_stage |        135 |        135 |       0 |    0 |   173 |      0 |      0 |            0 |
+|     if_stage                             |                     if_stage |        134 |        134 |       0 |    0 |   173 |      0 |      0 |            0 |
-|     mem_stage                            |                    mem_stage |        116 |        116 |       0 |    0 |   211 |      0 |      0 |            0 |
+|     mem_stage                            |                    mem_stage |        115 |        115 |       0 |    0 |   211 |      0 |      0 |            0 |
-|     u_csr                                |                          csr |        200 |        200 |       0 |    0 |   663 |      0 |      0 |            0 |
+|     u_csr                                |                          csr |        201 |        201 |       0 |    0 |   663 |      0 |      0 |            0 |
-|     u_div                                |                          div |        142 |        142 |       0 |    0 |   107 |      0 |      0 |            0 |
+|     u_div                                |                          div |        141 |        141 |       0 |    0 |   107 |      0 |      0 |            0 |
-|     u_mul                                |                          mul |        936 |        936 |       0 |    0 |   592 |      0 |      0 |            0 |
+|     u_mul                                |                          mul |        938 |        938 |       0 |    0 |   592 |      0 |      0 |            0 |
-|     wb_stage                             |                     wb_stage |        680 |        680 |       0 |    0 |   233 |      0 |      0 |            0 |
+|     wb_stage                             |                     wb_stage |        682 |        682 |       0 |    0 |   233 |      0 |      0 |            0 |
-|   u_fft_mlkem_axi_slave                  |          fft_mlkem_axi_slave |      36148 |      34927 |     112 | 1109 | 27165 |      8 |     10 |           16 |
+|   u_fft_mlkem_axi_slave                  |          fft_mlkem_axi_slave |      30142 |      28868 |     112 | 1162 | 18251 |     10 |     18 |            0 |
-|     (u_fft_mlkem_axi_slave)              |          fft_mlkem_axi_slave |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     (u_fft_mlkem_axi_slave)              |          fft_mlkem_axi_slave |          0 |          0 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     u_fft_controller                     |               fft_controller |       2646 |       1606 |       0 | 1040 |  1083 |      6 |      4 |           16 |
+|     u_fft_controller                     |               fft_controller |       6934 |       5894 |       0 | 1040 |  1083 |      8 |      4 |            0 |
-|       (u_fft_controller)                 |               fft_controller |        123 |        123 |       0 |    0 |   100 |      0 |      0 |            0 |
+|       (u_fft_controller)                 |               fft_controller |        118 |        118 |       0 |    0 |   100 |      0 |      0 |            0 |
-|       u_FFT                              |                          FFT |       2496 |       1456 |       0 | 1040 |   983 |      6 |      0 |           16 |
+|       u_FFT                              |                          FFT |       6782 |       5742 |       0 | 1040 |   983 |      8 |      0 |            0 |
-|         SU1                              |                      SdfUnit |       1071 |        303 |       0 |  768 |   197 |      2 |      0 |            4 |
+|         SU1                              |                      SdfUnit |       2144 |       1376 |       0 |  768 |   197 |      2 |      0 |            0 |
-|           (SU1)                          |                      SdfUnit |        205 |        205 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           (SU1)                          |                      SdfUnit |         39 |         39 |       0 |    0 |   133 |      0 |      0 |            0 |
-|           BF1                            |                 Butterfly_24 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_34 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            | Butterfly__parameterized0_25 |         33 |         33 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_35 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           DB1                            |                  DelayBuffer |        562 |         50 |       0 |  512 |    32 |      0 |      0 |            0 |
+|           DB1                            |                  DelayBuffer |        624 |        112 |       0 |  512 |    32 |      0 |      0 |            0 |
-|           DB2                            |  DelayBuffer__parameterized0 |        256 |          0 |       0 |  256 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized0 |        320 |         64 |       0 |  256 |    32 |      0 |      0 |            0 |
-|           MU                             |                  Multiply_26 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            4 |
+|           MU                             |                  Multiply_36 |        610 |        610 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           TW                             |                   Twiddle_27 |          1 |          1 |       0 |    0 |     0 |      2 |      0 |            0 |
+|           TW                             |                   Twiddle_37 |        543 |        543 |       0 |    0 |     0 |      2 |      0 |            0 |
-|         SU2                              |      SdfUnit__parameterized0 |        492 |        300 |       0 |  192 |   197 |      2 |      0 |            4 |
+|         SU2                              |      SdfUnit__parameterized0 |       1567 |       1375 |       0 |  192 |   197 |      2 |      0 |            0 |
-|           (SU2)                          |      SdfUnit__parameterized0 |         73 |         73 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           (SU2)                          |      SdfUnit__parameterized0 |         38 |         38 |       0 |    0 |   133 |      0 |      0 |            0 |
-|           BF1                            |                 Butterfly_20 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_30 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            | Butterfly__parameterized0_21 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_31 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
 |           DB1                            |  DelayBuffer__parameterized1 |        240 |        112 |       0 |  128 |    32 |      0 |      0 |            0 |
 |           DB2                            |  DelayBuffer__parameterized2 |        128 |         64 |       0 |   64 |    32 |      0 |      0 |            0 |
-|           MU                             |                  Multiply_22 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
+|           MU                             |                  Multiply_32 |        612 |        612 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           TW                             |                   Twiddle_23 |          3 |          3 |       0 |    0 |     0 |      2 |      0 |            0 |
+|           TW                             |                   Twiddle_33 |        541 |        541 |       0 |    0 |     0 |      2 |      0 |            0 |
-|         SU3                              |      SdfUnit__parameterized1 |        346 |        298 |       0 |   48 |   197 |      0 |      0 |            4 |
+|         SU3                              |      SdfUnit__parameterized1 |       1416 |       1368 |       0 |   48 |   197 |      2 |      0 |            0 |
-|           (SU3)                          |      SdfUnit__parameterized1 |         74 |         74 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           (SU3)                          |      SdfUnit__parameterized1 |         35 |         35 |       0 |    0 |   133 |      0 |      0 |            0 |
-|           BF1                            |                 Butterfly_17 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_26 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            | Butterfly__parameterized0_18 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_27 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
 |           DB1                            |  DelayBuffer__parameterized3 |        144 |        112 |       0 |   32 |    32 |      0 |      0 |            0 |
 |           DB2                            |  DelayBuffer__parameterized4 |         80 |         64 |       0 |   16 |    32 |      0 |      0 |            0 |
-|           MU                             |                  Multiply_19 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
+|           MU                             |                  Multiply_28 |        610 |        610 |       0 |    0 |     0 |      0 |      0 |            0 |
-|         SU4                              |      SdfUnit__parameterized2 |        327 |        295 |       0 |   32 |   197 |      2 |      0 |            4 |
+|           TW                             |                   Twiddle_29 |        539 |        539 |       0 |    0 |     0 |      2 |      0 |            0 |
-|           (SU4)                          |      SdfUnit__parameterized2 |         69 |         69 |       0 |    0 |   133 |      0 |      0 |            0 |
+|         SU4                              |      SdfUnit__parameterized2 |       1397 |       1365 |       0 |   32 |   197 |      2 |      0 |            0 |
-|           BF1                            |                 Butterfly_15 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           (SU4)                          |      SdfUnit__parameterized2 |         34 |         34 |       0 |    0 |   133 |      0 |      0 |            0 |
-|           BF2                            | Butterfly__parameterized0_16 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_24 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_25 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
 |           DB1                            |  DelayBuffer__parameterized5 |        128 |        112 |       0 |   16 |    32 |      0 |      0 |            0 |
 |           DB2                            |  DelayBuffer__parameterized6 |         80 |         64 |       0 |   16 |    32 |      0 |      0 |            0 |
-|           MU                             |                     Multiply |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
+|           MU                             |                     Multiply |        611 |        611 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           TW                             |                      Twiddle |          2 |          2 |       0 |    0 |     0 |      2 |      0 |            0 |
+|           TW                             |                      Twiddle |        536 |        536 |       0 |    0 |     0 |      2 |      0 |            0 |
-|         SU5                              |      SdfUnit__parameterized3 |        260 |        260 |       0 |    0 |   195 |      0 |      0 |            0 |
+|         SU5                              |      SdfUnit__parameterized3 |        258 |        258 |       0 |    0 |   195 |      0 |      0 |            0 |
-|           (SU5)                          |      SdfUnit__parameterized3 |         68 |         68 |       0 |    0 |    99 |      0 |      0 |            0 |
+|           (SU5)                          |      SdfUnit__parameterized3 |         34 |         34 |       0 |    0 |    99 |      0 |      0 |            0 |
 |           BF1                            |                    Butterfly |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            |    Butterfly__parameterized0 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            |    Butterfly__parameterized0 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
 |           DB1                            |  DelayBuffer__parameterized7 |        112 |        112 |       0 |    0 |    64 |      0 |      0 |            0 |
 |           DB2                            |  DelayBuffer__parameterized8 |         64 |         64 |       0 |    0 |    32 |      0 |      0 |            0 |
-|       u_in0                              |                     my_bram0 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_in0                              |                     my_bram0 |          2 |          2 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       u_in1                              |                  my_bram0_12 |          2 |          2 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_in1                              |                  my_bram0_21 |          2 |          2 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       u_out0                             |                  my_bram0_13 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_out0                             |                  my_bram0_22 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       u_out1                             |                  my_bram0_14 |         25 |         25 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_out1                             |                  my_bram0_23 |         32 |         32 |       0 |    0 |     0 |      0 |      1 |            0 |
-|     u_mlkem_axi_cdc                      |                    Axi_CDC_5 |        421 |        309 |     112 |    0 |   272 |      0 |      0 |            0 |
+|     u_mlkem_axi_cdc                      |                    Axi_CDC_5 |        336 |        224 |     112 |    0 |   272 |      0 |      0 |            0 |
-|       arFifo                             |               StreamFifoCC_3 |         53 |         25 |      28 |    0 |    55 |      0 |      0 |            0 |
+|       arFifo                             |               StreamFifoCC_3 |         50 |         22 |      28 |    0 |    55 |      0 |      0 |            0 |
-|         (arFifo)                         |               StreamFifoCC_3 |         44 |         16 |      28 |    0 |    43 |      0 |      0 |            0 |
+|         (arFifo)                         |               StreamFifoCC_3 |         42 |         14 |      28 |    0 |    43 |      0 |      0 |            0 |
-|         popToPushGray_buffercc           |                BufferCC_9_10 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                BufferCC_9_19 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         pushToPopGray_buffercc           |               BufferCC_11_11 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |               BufferCC_11_20 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       awFifo                             |                 StreamFifoCC |         40 |         16 |      24 |    0 |    49 |      0 |      0 |            0 |
+|       awFifo                             |                 StreamFifoCC |         39 |         15 |      24 |    0 |    49 |      0 |      0 |            0 |
 |         (awFifo)                         |                 StreamFifoCC |         31 |          7 |      24 |    0 |    35 |      0 |      0 |            0 |
 |         bufferCC_12                      |                  BufferCC_10 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|         popToPushGray_buffercc           |                   BufferCC_9 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                   BufferCC_9 |          3 |          3 |       0 |    0 |     6 |      0 |      0 |            0 |
 |         pushToPopGray_buffercc           |                  BufferCC_11 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
 |       bFifo                              |               StreamFifoCC_2 |         18 |         14 |       4 |    0 |    27 |      0 |      0 |            0 |
 |         (bFifo)                          |               StreamFifoCC_2 |         11 |          7 |       4 |    0 |    13 |      0 |      0 |            0 |
 |         bufferCC_12                      |                   BufferCC_5 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
 |         popToPushGray_buffercc           |                   BufferCC_4 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
 |         pushToPopGray_buffercc           |                   BufferCC_6 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       rFifo                              |               StreamFifoCC_4 |         57 |         29 |      28 |    0 |    72 |      0 |      0 |            0 |
+|       rFifo                              |               StreamFifoCC_4 |         65 |         37 |      28 |    0 |    72 |      0 |      0 |            0 |
-|         (rFifo)                          |               StreamFifoCC_4 |         49 |         21 |      28 |    0 |    56 |      0 |      0 |            0 |
+|         (rFifo)                          |               StreamFifoCC_4 |         58 |         30 |      28 |    0 |    56 |      0 |      0 |            0 |
-|         popToPushGray_buffercc           |                     BufferCC |          4 |          4 |       0 |    0 |     8 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                     BufferCC |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
 |         pushToPopGray_buffercc           |                   BufferCC_1 |          5 |          5 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       wFifo                              |               StreamFifoCC_1 |        253 |        225 |      28 |    0 |    69 |      0 |      0 |            0 |
+|       wFifo                              |               StreamFifoCC_1 |        164 |        136 |      28 |    0 |    69 |      0 |      0 |            0 |
-|         (wFifo)                          |               StreamFifoCC_1 |        248 |        220 |      28 |    0 |    53 |      0 |      0 |            0 |
+|         (wFifo)                          |               StreamFifoCC_1 |        159 |        131 |      28 |    0 |    53 |      0 |      0 |            0 |
 |         popToPushGray_buffercc           |                   BufferCC_7 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
 |         pushToPopGray_buffercc           |                   BufferCC_8 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
-|     u_mlkem_axi_slave                    |              mlkem_axi_slave |      33082 |      33013 |       0 |   69 | 25804 |      2 |      6 |            0 |
+|     u_mlkem_axi_slave                    |              mlkem_axi_slave |      22873 |      22751 |       0 |  122 | 16890 |      2 |     14 |            0 |
-|       (u_mlkem_axi_slave)                |              mlkem_axi_slave |       1202 |       1202 |       0 |    0 |  1068 |      0 |      0 |            0 |
+|       (u_mlkem_axi_slave)                |              mlkem_axi_slave |       1179 |       1179 |       0 |    0 |  1064 |      0 |      0 |            0 |
-|       u_mlkem                            |                    mlkem_top |      31884 |      31815 |       0 |   69 | 24736 |      2 |      6 |            0 |
+|       u_mlkem                            |                    mlkem_top |      21697 |      21575 |       0 |  122 | 15826 |      2 |     14 |            0 |
-|         (u_mlkem)                        |                    mlkem_top |       2738 |       2738 |       0 |    0 |  4960 |      0 |      0 |            0 |
+|         (u_mlkem)                        |                    mlkem_top |       2633 |       2633 |       0 |    0 |  5010 |      0 |      0 |            0 |
-|         u_bank_a                         |      sd_bram__parameterized0 |         50 |         50 |       0 |    0 |     0 |      1 |      1 |            0 |
+|         u_bank_a                         |      sd_bram__parameterized0 |         61 |         61 |       0 |    0 |     0 |      1 |      1 |            0 |
-|         u_bank_se                        |      sd_bram__parameterized1 |         70 |         70 |       0 |    0 |     0 |      1 |      0 |            0 |
+|         u_bank_se                        |      sd_bram__parameterized1 |         77 |         77 |       0 |    0 |     0 |      1 |      0 |            0 |
-|         u_bank_t                         |      sd_bram__parameterized2 |        654 |        654 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_bank_t                         |      sd_bram__parameterized2 |        632 |        632 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_c_in_bram                      |                      sd_bram |       1312 |       1312 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_c_in_bram                      |                      sd_bram |       1301 |       1301 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_cbd                            |       sample_cbd_sync_shared |       2741 |       2741 |       0 |    0 |  3186 |      0 |      0 |            0 |
+|         u_cbd                            |       sample_cbd_sync_shared |       2739 |       2739 |       0 |    0 |  3186 |      0 |      0 |            0 |
-|         u_comp                           |             comp_decomp_sync |        467 |        466 |       0 |    1 |   323 |      0 |      0 |            0 |
+|         u_comp                           |             comp_decomp_sync |        620 |        618 |       0 |    2 |   319 |      0 |      0 |            0 |
-|         u_ct_bram                        |                    sd_bram_6 |         13 |         13 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_ct_bram                        |                    sd_bram_6 |         10 |         10 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_dkp_bram                       |                    sd_bram_7 |         82 |         82 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_dkp_bram                       |                    sd_bram_7 |         74 |         74 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_ek_bram                        |                    sd_bram_8 |       2121 |       2121 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_ek_bram                        |                    sd_bram_8 |        304 |        304 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_keccak                         |                  keccak_core |       5274 |       5274 |       0 |    0 |  1606 |      0 |      0 |            0 |
+|         u_keccak                         |                  keccak_core |       5258 |       5258 |       0 |    0 |  1618 |      0 |      0 |            0 |
-|         u_ntt                            |                     ntt_core |       8625 |       8582 |       0 |   43 |  3861 |      0 |      0 |            0 |
+|         u_ntt                            |                     ntt_core |       1900 |       1817 |       0 |   83 |  1062 |      0 |      4 |            0 |
-|           (u_ntt)                        |                     ntt_core |       6101 |       6085 |       0 |   16 |  3358 |      0 |      0 |            0 |
+|           (u_ntt)                        |                     ntt_core |        281 |        249 |       0 |   32 |   215 |      0 |      0 |            0 |
-|           u_bf                           |          butterfly_unit_pipe |       2260 |       2234 |       0 |   26 |   286 |      0 |      0 |            0 |
+|           u_bf0                          |          butterfly_unit_pipe |        675 |        650 |       0 |   25 |   321 |      0 |      0 |            0 |
-|             (u_bf)                       |          butterfly_unit_pipe |         69 |         44 |       0 |   25 |    75 |      0 |      0 |            0 |
+|             (u_bf0)                      |          butterfly_unit_pipe |        264 |        239 |       0 |   25 |   112 |      0 |      0 |            0 |
-|             u_barrett                    |           barrett_mul_pipe_9 |       2192 |       2191 |       0 |    1 |   211 |      0 |      0 |            0 |
+|             u_barrett                    |          barrett_mul_pipe_18 |        411 |        411 |       0 |    0 |   209 |      0 |      0 |            0 |
-|           u_scl                          |             barrett_mul_pipe |        265 |        264 |       0 |    1 |   217 |      0 |      0 |            0 |
+|           u_bf1                          |       butterfly_unit_pipe_12 |        487 |        462 |       0 |   25 |   307 |      0 |      0 |            0 |
-|         u_pmul                           |                poly_mul_sync |       3881 |       3856 |       0 |   25 |  6743 |      0 |      0 |            0 |
+|             (u_bf1)                      |       butterfly_unit_pipe_12 |         89 |         65 |       0 |   24 |    96 |      0 |      0 |            0 |
-|           (u_pmul)                       |                poly_mul_sync |       2434 |       2434 |       0 |    0 |  6280 |      0 |      0 |            0 |
+|             u_barrett                    |          barrett_mul_pipe_17 |        398 |        397 |       0 |    1 |   211 |      0 |      0 |            0 |
-|           u_bc                           |            basecase_mul_pipe |       1447 |       1422 |       0 |   25 |   463 |      0 |      0 |            0 |
+|           u_cr                           |              coeff_bram_4way |        208 |        208 |       0 |    0 |     8 |      0 |      4 |            0 |
-|         u_sha3                           |              sha3_top_shared |       1766 |       1766 |       0 |    0 |  2388 |      0 |      0 |            0 |
+|             (u_cr)                       |              coeff_bram_4way |          6 |          6 |       0 |    0 |     8 |      0 |      0 |            0 |
+|             gen_xbar[0].u_bank           |   sd_bram__parameterized3_13 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
+|             gen_xbar[1].u_bank           |   sd_bram__parameterized3_14 |         89 |         89 |       0 |    0 |     0 |      0 |      1 |            0 |
+|             gen_xbar[2].u_bank           |   sd_bram__parameterized3_15 |         16 |         16 |       0 |    0 |     0 |      0 |      1 |            0 |
+|             gen_xbar[3].u_bank           |   sd_bram__parameterized3_16 |         82 |         82 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_scl                          |             barrett_mul_pipe |        252 |        251 |       0 |    1 |   211 |      0 |      0 |            0 |
+|         u_pmul                           |                poly_mul_sync |       2058 |       2021 |       0 |   37 |   584 |      0 |      4 |            0 |
+|           (u_pmul)                       |                poly_mul_sync |        634 |        634 |       0 |    0 |   121 |      0 |      0 |            0 |
+|           u_a_even                       |      sd_bram__parameterized3 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_a_odd                        |    sd_bram__parameterized3_9 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_b_even                       |   sd_bram__parameterized3_10 |          1 |          1 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_b_odd                        |   sd_bram__parameterized3_11 |          1 |          1 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_bc                           |            basecase_mul_pipe |       1423 |       1386 |       0 |   37 |   463 |      0 |      0 |            0 |
+|         u_sha3                           |              sha3_top_shared |       1955 |       1955 |       0 |    0 |  2378 |      0 |      0 |            0 |
 |         u_snt                            |       sample_ntt_sync_shared |       2109 |       2109 |       0 |    0 |  1669 |      0 |      0 |            0 |
-|   u_matmul_axi_slave                     |             matmul_axi_slave |       9758 |       9576 |     176 |    6 |  3248 |      0 |      0 |            0 |
+|   u_matmul_axi_slave                     |             matmul_axi_slave |       9879 |       9697 |     176 |    6 |  3243 |      0 |      0 |            0 |
-|     (u_matmul_axi_slave)                 |             matmul_axi_slave |       5637 |       5455 |     176 |    6 |  2480 |      0 |      0 |            0 |
+|     (u_matmul_axi_slave)                 |             matmul_axi_slave |       5761 |       5579 |     176 |    6 |  2475 |      0 |      0 |            0 |
-|     mult_inst[0].u_mult                  |         pipelined_mult_32x32 |       1063 |       1063 |       0 |    0 |   192 |      0 |      0 |            0 |
+|     mult_inst[0].u_mult                  |         pipelined_mult_32x32 |       1062 |       1062 |       0 |    0 |   192 |      0 |      0 |            0 |
 |     mult_inst[1].u_mult                  |       pipelined_mult_32x32_2 |        999 |        999 |       0 |    0 |   192 |      0 |      0 |            0 |
-|     mult_inst[2].u_mult                  |       pipelined_mult_32x32_3 |       1062 |       1062 |       0 |    0 |   192 |      0 |      0 |            0 |
+|     mult_inst[2].u_mult                  |       pipelined_mult_32x32_3 |       1060 |       1060 |       0 |    0 |   192 |      0 |      0 |            0 |
 |     mult_inst[3].u_mult                  |       pipelined_mult_32x32_4 |        997 |        997 |       0 |    0 |   192 |      0 |      0 |            0 |
-|   u_snix_axil_cdma_mux_8ch               |           snix_axil_cdma_mux |       1788 |       1788 |       0 |    0 |  1476 |      0 |      1 |            0 |
+|   u_snix_axil_cdma_mux_8ch               |           snix_axil_cdma_mux |       1557 |       1557 |       0 |    0 |  1476 |      0 |      1 |            0 |
-|     (u_snix_axil_cdma_mux_8ch)           |           snix_axil_cdma_mux |        751 |        751 |       0 |    0 |  1180 |      0 |      0 |            0 |
+|     (u_snix_axil_cdma_mux_8ch)           |           snix_axil_cdma_mux |        600 |        600 |       0 |    0 |  1180 |      0 |      0 |            0 |
-|     u_core_engine                        |               snix_axi_mm2mm |       1038 |       1038 |       0 |    0 |   296 |      0 |      1 |            0 |
+|     u_core_engine                        |               snix_axi_mm2mm |        960 |        960 |       0 |    0 |   296 |      0 |      1 |            0 |
-|       (u_core_engine)                    |               snix_axi_mm2mm |        762 |        762 |       0 |    0 |   243 |      0 |      0 |            0 |
+|       (u_core_engine)                    |               snix_axi_mm2mm |        750 |        750 |       0 |    0 |   243 |      0 |      0 |            0 |
-|       axis_fifo_u0                       |               snix_axis_fifo |        276 |        276 |       0 |    0 |    53 |      0 |      1 |            0 |
+|       axis_fifo_u0                       |               snix_axis_fifo |        210 |        210 |       0 |    0 |    53 |      0 |      1 |            0 |
-|         u_fifo                           |               snix_sync_fifo |        276 |        276 |       0 |    0 |    53 |      0 |      1 |            0 |
+|         u_fifo                           |               snix_sync_fifo |        210 |        210 |       0 |    0 |    53 |      0 |      1 |            0 |
 +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
 * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
 

fpga/vivado_reports_nodsp/vivado_reports_nodsp/clock_interaction.rpt

@@ -1,28 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:13 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt
-| Design       : soc_top
-| Device       : 7a200t-fbg676
-| Speed File   : -1  PRODUCTION 1.23 2018-06-13
-------------------------------------------------------------------------------------------------------------
-
-Clock Interaction Report
-
-Clock Interaction Table
------------------------
-
-                                      WNS                            TNS Failing  TNS Total    WNS Path         Clock-Pair           Inter-Clock          
-From Clock         To Clock           Clock Edges  WNS(ns)  TNS(ns)    Endpoints    Endpoints  Requirement(ns)  Classification       Constraints          
------------------  -----------------  -----------  -------  -------  -----------  -----------  ---------------  -------------------  -------------------  
-cpu_clk            cpu_clk            rise - rise     2.72     0.00            0        17264            30.32  Clean                Timed                
-cpu_clk            sys_clk                                                     0          162                   Ignored              Asynchronous Groups  
-mlkem_clk_clk_pll  mlkem_clk_clk_pll  rise - rise    10.81     0.00            0        74168            40.00  Clean                Timed                
-mlkem_clk_clk_pll  sys_clk            rise - rise    11.25     0.00            0           61            20.00  Clean                Timed                
-sys_clk            cpu_clk                                                     0           59                   Ignored              Asynchronous Groups  
-sys_clk            mlkem_clk_clk_pll  rise - rise     9.16     0.00            0          112            20.00  Clean                Timed                
-sys_clk            sys_clk            rise - rise     0.17     0.00            0        23704            20.00  Clean                Timed                
-
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/clocks.rpt

@@ -1,76 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:13 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt
-| Design       : soc_top
-| Device       : 7a200t-fbg676
-| Speed File   : -1  PRODUCTION 1.23 2018-06-13
---------------------------------------------------------------------------------------
-
-Clock Report
-
-
-Attributes
-  P: Propagated
-  G: Generated
-  A: Auto-derived
-  R: Renamed
-  V: Virtual
-  I: Inverted
-  S: Pin phase-shifted with Latency mode
-
-Clock              Period(ns)  Waveform(ns)    Attributes  Sources
-clk                20.000      {0.000 10.000}  P           {clk}
-clkfbout_clk_pll   20.000      {0.000 10.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
-cpu_clk            30.323      {0.000 15.161}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
-mlkem_clk_clk_pll  40.000      {0.000 20.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
-sys_clk            20.000      {0.000 10.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
-
-
-====================================================
-Generated Clocks
-====================================================
-
-Generated Clock     : clkfbout_clk_pll
-Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
-Master Clock        : clk
-Multiply By         : 1
-Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
-
-Generated Clock     : cpu_clk
-Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
-Master Clock        : clk
-Edges               : {1 2 3}
-Edge Shifts(ns)     : {0.000 5.161 10.323}
-Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
-
-Generated Clock     : mlkem_clk_clk_pll
-Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
-Master Clock        : clk
-Edges               : {1 2 3}
-Edge Shifts(ns)     : {0.000 10.000 20.000}
-Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
-
-Generated Clock     : sys_clk
-Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
-Master Clock        : clk
-Multiply By         : 1
-Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
-
-
-
-====================================================
-User Uncertainty
-====================================================
-
-
-
-====================================================
-User Jitter
-====================================================
-
-Clock  Jitter(ns)
-clk    0.200
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_complexity.rpt

@@ -1,37 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:35:00 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt
-| Design       : soc_top
-| Device       : xc7a200t
-| Design State : Routed
--------------------------------------------------------------------------------------------------------------------------------
-
-Report Design Analysis
-
-Table of Contents
------------------
-1. Complexity Characteristics (Cells)
-
-1. Complexity Characteristics (Cells)
--------------------------------------
-
-+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
-|          Instance         |        Module       | Rent | Average Fanout | Total Instances |    LUT1   |     LUT2    |     LUT3    |     LUT4    |     LUT5    |     LUT6     | Memory LUT | DSP | RAMB | MUXF | URAM |
-+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
-| (top)                     |             soc_top | 0.34 |           3.77 |          118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) |       1175 |  16 |   39 | 6020 |    0 |
-|  u_axi_axil_adapter       |    axi_axil_adapter | 0.50 |           5.92 |            1309 |   0(0.0%) |     8(0.7%) |    43(3.8%) |   100(8.9%) |  200(17.7%) |   776(68.9%) |          0 |   0 |    0 |    0 |    0 |
-|  u_axi_uart_controller    | axi_uart_controller | 0.55 |           3.54 |            1296 |  10(1.2%) |   84(10.4%) |    80(9.9%) |  144(17.9%) |  194(24.1%) |   293(36.4%) |          0 |   0 |    0 |    9 |    0 |
-|  u_cdma_matmul_bridge     |  cdma_matmul_bridge | 0.46 |           2.22 |            1002 |   1(0.3%) |   65(17.1%) |   39(10.3%) |  174(45.8%) |    13(3.4%) |    88(23.2%) |          0 |   0 |    0 |    0 |    0 |
-|  u_cpu                    |            core_top | 0.56 |           3.96 |           15822 | 168(1.8%) |   579(6.3%) | 1029(11.1%) |   871(9.4%) | 1744(18.9%) |  4860(52.5%) |          0 |   0 |   20 |  276 |    0 |
-|  u_fft_mlkem_axi_slave    | fft_mlkem_axi_slave | 0.56 |           3.75 |           74954 | 362(0.9%) |  3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) |       1169 |  16 |   18 | 5286 |    0 |
-|  u_matmul_axi_slave       |    matmul_axi_slave | 0.63 |           3.76 |           15159 |  18(0.2%) | 1646(15.2%) |   357(3.3%) |   830(7.6%) |   974(9.0%) |  7026(64.7%) |          6 |   0 |    0 |  413 |    0 |
-|  u_snix_axil_cdma_mux_8ch |  snix_axil_cdma_mux | 0.36 |           3.45 |            3680 | 136(6.5%) |   181(8.6%) |  405(19.3%) |  255(12.2%) |  342(16.3%) |   776(37.0%) |          0 |   0 |    1 |    4 |    0 |
-+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
-* Complexity Ranges 
-** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal,  0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
-*** -* -> Not computable as cell size is very small
-
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_timing.rpt

@@ -1,52 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:29 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt
-| Design       : soc_top
-| Device       : xc7a200t
-| Design State : Routed
------------------------------------------------------------------------------------------------------------------------
-
-Report Design Analysis
-
-Table of Contents
------------------
-1. Setup Path Characteristics 1-1
-
-1. Setup Path Characteristics 1-1
----------------------------------
-
-+---------------------------+------------------------------------------------------+
-|      Characteristics      |                        Path #1                       |
-+---------------------------+------------------------------------------------------+
-| Requirement               |                                               20.000 |
-| Path Delay                |                                               15.605 |
-| Logic Delay               | 5.343(35%)                                           |
-| Net Delay                 | 10.263(65%)                                          |
-| Clock Skew                |                                               -3.858 |
-| Slack                     |                                                0.167 |
-| Clock Relationship        | Safely Timed                                         |
-| Logic Levels              |                                                    9 |
-| Routes                    |                                                    9 |
-| Logical Path              | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT |
-| Start Point Clock         | sys_clk                                              |
-| End Point Clock           | sys_clk                                              |
-| DSP Block                 | None                                                 |
-| BRAM                      | None                                                 |
-| IO Crossings              |                                                    3 |
-| Config Crossings          |                                                    0 |
-| SLR Crossings             |                                                    0 |
-| PBlocks                   |                                                    0 |
-| High Fanout               |                                                  130 |
-| Dont Touch                |                                                    0 |
-| Mark Debug                |                                                    0 |
-| Start Point Pin Primitive | FDRE/C                                               |
-| End Point Pin Primitive   | ext_ram_data[18]                                     |
-| Start Point Pin           | FSM_sequential_ext_wr_state_reg[1]/C                 |
-| End Point Pin             | ext_ram_data[18]                                     |
-+---------------------------+------------------------------------------------------+
-* Bounding box calculated as % of dimensions for the target device (436, 500)
-
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/drc.rpt

@@ -1,491 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:33:58 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt
-| Design       : soc_top
-| Device       : xc7a200tfbg676-1
-| Speed File   : -1
-| Design State : Fully Routed
-------------------------------------------------------------------------------------
-
-Report DRC
-
-Table of Contents
------------------
-1. REPORT SUMMARY
-2. REPORT DETAILS
-
-1. REPORT SUMMARY
------------------
-            Netlist: netlist
-          Floorplan: impl_1
-      Design limits: <entire design considered>
-           Ruledeck: default
-             Max violations: <unlimited>
-             Violations found: 90
-+-----------+----------+----------------------------+------------+
-| Rule      | Severity | Description                | Violations |
-+-----------+----------+----------------------------+------------+
-| CHECK-3   | Warning  | Report rule limit reached  | 2          |
-| DPIP-1    | Warning  | Input pipelining           | 16         |
-| DPOP-1    | Warning  | PREG Output pipelining     | 16         |
-| DPOP-2    | Warning  | MREG Output pipelining     | 16         |
-| REQP-1839 | Warning  | RAMB36 async control check | 20         |
-| REQP-1840 | Warning  | RAMB18 async control check | 20         |
-+-----------+----------+----------------------------+------------+
-
-2. REPORT DETAILS
------------------
-CHECK-3#1 Warning
-Report rule limit reached  
-REQP-1839 rule limit reached: 20 violations have been found.
-Related violations: <none>
-
-CHECK-3#2 Warning
-Report rule limit reached  
-REQP-1840 rule limit reached: 20 violations have been found.
-Related violations: <none>
-
-DPIP-1#1 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#2 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#3 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#4 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#5 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#6 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#7 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#8 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#9 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#10 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#11 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#12 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#13 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#14 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#15 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPIP-1#16 Warning
-Input pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: <none>
-
-DPOP-1#1 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#2 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#3 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#4 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#5 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#6 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#7 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#8 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#9 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#10 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#11 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#12 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#13 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#14 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#15 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-1#16 Warning
-PREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
-Related violations: <none>
-
-DPOP-2#1 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#2 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#3 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#4 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#5 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#6 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#7 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#8 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#9 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#10 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#11 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#12 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#13 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#14 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#15 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-DPOP-2#16 Warning
-MREG Output pipelining  
-DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-Related violations: <none>
-
-REQP-1839#1 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#2 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#3 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#4 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#5 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#6 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#7 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#8 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#9 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#10 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#11 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#12 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#13 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#14 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#15 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#16 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#17 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#18 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#19 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1839#20 Warning
-RAMB36 async control check  
-The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#1 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#2 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#3 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#4 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#5 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#6 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#7 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#8 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#9 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#10 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#11 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#12 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#13 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#14 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#15 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#16 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#17 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#18 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#19 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-REQP-1840#20 Warning
-RAMB18 async control check  
-The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
-Related violations: <none>
-
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/high_fanout.rpt

@@ -1,221 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:13 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt
-| Design       : soc_top
-| Device       : xc7a200t
---------------------------------------------------------------------------------------------------------------------------------------------
-
-High Fan-out Nets Information
-
-1. Summary
-----------
-
-+---------------------------------------------------------------------------------------+--------+-------------+
-| Net Name                                                                              | Fanout | Driver Type |
-+---------------------------------------------------------------------------------------+--------+-------------+
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1]                |  24598 | LUT5        |
-| pll_clk.u_clk_pll/inst/sys_clk                                                        |  10004 | BUFG        |
-| pll_clk.u_rst_sys/p_0_in                                                              |   4130 | LUT1        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0]                         |   2048 | LUT2        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0               |   1619 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0]              |   1608 | LUT2        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0               |   1608 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 |   1604 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd                      |   1603 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0        |   1601 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0           |   1601 | LUT6        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0           |   1601 | LUT6        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0           |   1601 | LUT6        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0       |   1600 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1]                   |   1543 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2]                   |   1542 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1                 |   1109 | LUT2        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0                     |   1088 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0                     |   1088 | FDRE        |
-| pll_clk.u_rst_mlkem/delay_reg[1]_0                                                    |   1069 | LUT1        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0                           |    936 | LUT5        |
-| u_cpu/reset                                                                           |    799 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0]  |    769 | CARRY4      |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1]  |    769 | CARRY4      |
-| u_matmul_axi_slave/w_addr[2]                                                          |    724 | FDRE        |
-| u_cpu/u_mul/E[0]                                                                      |    716 | LUT1        |
-| u_matmul_axi_slave/w_addr[3]                                                          |    628 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1                                  |    528 | LUT6        |
-| u_matmul_axi_slave/current_r_offset[2]                                                |    522 | LUT5        |
-| u_matmul_axi_slave/current_r_offset[3]                                                |    520 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0]                   |    516 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1]                   |    516 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0              |    512 | LUT2        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0]             |    512 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2]             |    390 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2]  |    385 | CARRY4      |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0                      |    370 | FDCE        |
-| u_cpu/wb_stage/w_index[0]                                                             |    358 | LUT6        |
-| u_cpu/wb_stage/w_index[1]                                                             |    358 | LUT6        |
-| u_cpu/wb_stage/w_index[2]                                                             |    358 | LUT6        |
-| u_cpu/wb_stage/w_index[3]                                                             |    358 | LUT6        |
-| u_cpu/wb_stage/w_index[4]                                                             |    358 | LUT6        |
-| u_matmul_axi_slave/acc_idx_d4[0]                                                      |    354 | FDRE        |
-| u_matmul_axi_slave/acc_idx_d4[1]                                                      |    354 | FDRE        |
-| u_matmul_axi_slave/acc_idx_d4[2]                                                      |    354 | FDRE        |
-| u_matmul_axi_slave/acc_idx_d4[3]                                                      |    354 | FDRE        |
-| u_cpu/wb_stage/we_0                                                                   |    324 | LUT4        |
-| u_matmul_axi_slave/w_addr[4]                                                          |    317 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1                         |    290 | LUT6        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3]                      |    284 | FDCE        |
-| u_matmul_axi_slave/cur_bank_reg_n_0                                                   |    277 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10]                  |    263 | RAMB18E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11]                  |    263 | RAMB18E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8]                   |    262 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7]                   |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9]                   |    261 | RAMB18E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10]                   |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11]                   |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9]                    |    261 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc                      |    261 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4]                    |    260 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0]                   |    259 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1]                   |    259 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2]                   |    259 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3]                   |    259 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4]                   |    259 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5]                   |    259 | RAMB36E1    |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6]                   |    259 | RAMB36E1    |
-| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0                                            |    259 | FDRE        |
-| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0                                            |    257 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10]                   |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11]                   |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9]                    |    256 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0]        |    256 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r                    |    256 | LUT3        |
-| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0                                              |    256 | LUT6        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode                    |    250 | LUT4        |
-| u_matmul_axi_slave/w_addr[5]                                                          |    246 | FDRE        |
-| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge                                  |    245 | LUT3        |
-| u_cpu/exe_stage/ds_to_es_bus_r0                                                       |    234 | LUT5        |
-| u_cpu/mem_stage/E[0]                                                                  |    234 | LUT6        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10]                 |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11]                 |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10]                 |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11]                 |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8]                  |    234 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9]                  |    234 | FDCE        |
-| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 |    229 | LUT3        |
-| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0                                              |    228 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1]                      |    227 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0              |    224 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0               |    224 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0               |    224 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0               |    224 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0               |    224 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0               |    224 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0               |    224 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0               |    224 | LUT4        |
-| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0                            |    211 | LUT2        |
-| u_cpu/mem_stage/es_to_ms_bus_r0                                                       |    210 | LUT2        |
-| u_cpu/u_csr/tlbw_r_tlbidx[2]                                                          |    210 | FDRE        |
-| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0]                                           |    203 | FDRE        |
-| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1]                                           |    203 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6]                      |    200 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4]                      |    200 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3]             |    197 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2]           |    196 | FDCE        |
-| u_snix_axil_cdma_mux_8ch/ADDRA[0]                                                     |    196 | LUT6        |
-| u_cpu/wb_stage/Q[33]                                                                  |    194 | FDRE        |
-| u_cpu/wb_stage/Q[34]                                                                  |    194 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5]             |    194 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3]  |    193 | CARRY4      |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0          |    191 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2]                     |    187 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3]                     |    187 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1]                      |    187 | FDCE        |
-| u_matmul_axi_slave/current_r_offset[4]                                                |    187 | LUT5        |
-| u_matmul_axi_slave/s_axi_wready_reg_1                                                 |    181 | LUT3        |
-| u_cpu/wb_stage/ws_valid_reg_0                                                         |    180 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3]                      |    180 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2]                             |    177 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0]                      |    176 | FDCE        |
-| u_matmul_axi_slave/p_0_in__0                                                          |    176 | LUT4        |
-| u_matmul_axi_slave/p_0_in__0__0                                                       |    176 | LUT4        |
-| u_cpu/wb_stage/Q[37]                                                                  |    173 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7]                      |    173 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7                     |    171 | CARRY4      |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0                |    169 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0                |    169 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0                |    169 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0                |    169 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]                                 |    169 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5]                    |    166 | FDCE        |
-| u_cpu/wb_stage/Q[32]                                                                  |    164 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0]                      |    164 | FDCE        |
-| u_cpu/wb_stage/Q[35]                                                                  |    163 | FDRE        |
-| u_cpu/wb_stage/Q[36]                                                                  |    162 | FDRE        |
-| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0                |    161 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0               |    160 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0                |    160 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0                |    160 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0                |    160 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3]                             |    155 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6]                     |    153 | FDCE        |
-| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0                                                |    153 | LUT3        |
-| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0                           |    151 | FDRE        |
-| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1                                |    150 | CARRY4      |
-| u_cpu/dcache/awaddr[31]_i_3_n_0                                                       |    148 | LUT2        |
-| u_cpu/dcache/awaddr[31]_i_4_n_0                                                       |    148 | LUT2        |
-| u_matmul_axi_slave/s_axi_wready_reg_0                                                 |    148 | LUT5        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0]                  |    145 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0                    |    144 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6]                            |    143 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6]                      |    143 | FDCE        |
-| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0                                                |    143 | LUT3        |
-| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0                                                |    143 | LUT3        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0                     |    142 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4]                            |    141 | FDCE        |
-| u_cpu/dcache/write_buffer_state                                                       |    140 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0              |    140 | FDCE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5]                            |    140 | FDCE        |
-| u_cpu/u_csr/tlbw_r_tlbidx[0]                                                          |    139 | FDRE        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0                      |    139 | LUT4        |
-| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0                  |    139 | FDCE        |
-+---------------------------------------------------------------------------------------+--------+-------------+
-
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/methodology.rpt

@@ -1,542 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:05 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt
-| Design       : soc_top
-| Device       : xc7a200tfbg676-1
-| Speed File   : -1
-| Design State : Fully Routed
-------------------------------------------------------------------------------------------------
-
-Report Methodology
-
-Table of Contents
------------------
-1. REPORT SUMMARY
-2. REPORT DETAILS
-
-1. REPORT SUMMARY
------------------
-            Netlist: netlist
-          Floorplan: impl_1
-      Design limits: <entire design considered>
-             Max violations: <unlimited>
-             Violations found: 99
-+-----------+----------+-------------------------------------------------------------------+------------+
-| Rule      | Severity | Description                                                       | Violations |
-+-----------+----------+-------------------------------------------------------------------+------------+
-| LUTAR-1   | Warning  | LUT drives async reset alert                                      | 1          |
-| SYNTH-5   | Warning  | Mapped onto distributed RAM because of timing constraints         | 8          |
-| SYNTH-6   | Warning  | Timing of a block RAM might be sub-optimal                        | 1          |
-| SYNTH-16  | Warning  | Address collision                                                 | 8          |
-| TIMING-10 | Warning  | Missing property on synchronizer                                  | 1          |
-| TIMING-18 | Warning  | Missing input or output delay                                     | 76         |
-| TIMING-47 | Warning  | False path or asynchronous clock group between synchronous clocks | 2          |
-| XDCC-1    | Warning  | Scoped Clock constraint overwritten with the same name            | 1          |
-| XDCC-7    | Warning  | Scoped Clock constraint overwritten on the same source            | 1          |
-+-----------+----------+-------------------------------------------------------------------+------------+
-
-2. REPORT DETAILS
------------------
-LUTAR-1#1 Warning
-LUT drives async reset alert  
-LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
-Related violations: <none>
-
-SYNTH-5#1 Warning
-Mapped onto distributed RAM because of timing constraints  
-The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
-Related violations: <none>
-
-SYNTH-5#2 Warning
-Mapped onto distributed RAM because of timing constraints  
-The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
-Related violations: <none>
-
-SYNTH-5#3 Warning
-Mapped onto distributed RAM because of timing constraints  
-The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
-Related violations: <none>
-
-SYNTH-5#4 Warning
-Mapped onto distributed RAM because of timing constraints  
-The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
-Related violations: <none>
-
-SYNTH-5#5 Warning
-Mapped onto distributed RAM because of timing constraints  
-The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
-Related violations: <none>
-
-SYNTH-5#6 Warning
-Mapped onto distributed RAM because of timing constraints  
-The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
-Related violations: <none>
-
-SYNTH-5#7 Warning
-Mapped onto distributed RAM because of timing constraints  
-The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
-Related violations: <none>
-
-SYNTH-5#8 Warning
-Mapped onto distributed RAM because of timing constraints  
-The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
-Related violations: <none>
-
-SYNTH-6#1 Warning
-Timing of a block RAM might be sub-optimal  
-The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
-Related violations: <none>
-
-SYNTH-16#1 Warning
-Address collision  
-Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
-Related violations: <none>
-
-SYNTH-16#2 Warning
-Address collision  
-Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
-Related violations: <none>
-
-SYNTH-16#3 Warning
-Address collision  
-Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
-Related violations: <none>
-
-SYNTH-16#4 Warning
-Address collision  
-Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
-Related violations: <none>
-
-SYNTH-16#5 Warning
-Address collision  
-Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
-Related violations: <none>
-
-SYNTH-16#6 Warning
-Address collision  
-Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
-Related violations: <none>
-
-SYNTH-16#7 Warning
-Address collision  
-Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
-Related violations: <none>
-
-SYNTH-16#8 Warning
-Address collision  
-Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
-Related violations: <none>
-
-TIMING-10#1 Warning
-Missing property on synchronizer  
-One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
-Related violations: <none>
-
-TIMING-18#1 Warning
-Missing input or output delay  
-An input delay is missing on UART_RX relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#2 Warning
-Missing input or output delay  
-An input delay is missing on UART_TX relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#3 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[0] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#4 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[10] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#5 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[11] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#6 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[12] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#7 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[13] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#8 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[14] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#9 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[15] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#10 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[16] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#11 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[17] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#12 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[18] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#13 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[19] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#14 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[1] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#15 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[20] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#16 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[21] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#17 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[22] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#18 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[23] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#19 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[24] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#20 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[25] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#21 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[26] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#22 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[27] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#23 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[28] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#24 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[29] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#25 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[2] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#26 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[30] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#27 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[31] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#28 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[3] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#29 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[4] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#30 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[5] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#31 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[6] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#32 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[7] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#33 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[8] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#34 Warning
-Missing input or output delay  
-An input delay is missing on dip_sw[9] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#35 Warning
-Missing input or output delay  
-An input delay is missing on touch_btn[0] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#36 Warning
-Missing input or output delay  
-An input delay is missing on touch_btn[1] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#37 Warning
-Missing input or output delay  
-An input delay is missing on touch_btn[2] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#38 Warning
-Missing input or output delay  
-An input delay is missing on touch_btn[3] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#39 Warning
-Missing input or output delay  
-An output delay is missing on dpy0[0] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#40 Warning
-Missing input or output delay  
-An output delay is missing on dpy0[1] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#41 Warning
-Missing input or output delay  
-An output delay is missing on dpy0[2] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#42 Warning
-Missing input or output delay  
-An output delay is missing on dpy0[3] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#43 Warning
-Missing input or output delay  
-An output delay is missing on dpy0[4] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#44 Warning
-Missing input or output delay  
-An output delay is missing on dpy0[5] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#45 Warning
-Missing input or output delay  
-An output delay is missing on dpy0[6] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#46 Warning
-Missing input or output delay  
-An output delay is missing on dpy0[7] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#47 Warning
-Missing input or output delay  
-An output delay is missing on dpy1[0] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#48 Warning
-Missing input or output delay  
-An output delay is missing on dpy1[1] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#49 Warning
-Missing input or output delay  
-An output delay is missing on dpy1[2] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#50 Warning
-Missing input or output delay  
-An output delay is missing on dpy1[3] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#51 Warning
-Missing input or output delay  
-An output delay is missing on dpy1[4] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#52 Warning
-Missing input or output delay  
-An output delay is missing on dpy1[5] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#53 Warning
-Missing input or output delay  
-An output delay is missing on dpy1[6] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#54 Warning
-Missing input or output delay  
-An output delay is missing on dpy1[7] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#55 Warning
-Missing input or output delay  
-An output delay is missing on leds[0] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#56 Warning
-Missing input or output delay  
-An output delay is missing on leds[10] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#57 Warning
-Missing input or output delay  
-An output delay is missing on leds[11] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#58 Warning
-Missing input or output delay  
-An output delay is missing on leds[12] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#59 Warning
-Missing input or output delay  
-An output delay is missing on leds[13] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#60 Warning
-Missing input or output delay  
-An output delay is missing on leds[14] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#61 Warning
-Missing input or output delay  
-An output delay is missing on leds[15] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#62 Warning
-Missing input or output delay  
-An output delay is missing on leds[1] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#63 Warning
-Missing input or output delay  
-An output delay is missing on leds[2] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#64 Warning
-Missing input or output delay  
-An output delay is missing on leds[3] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#65 Warning
-Missing input or output delay  
-An output delay is missing on leds[4] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#66 Warning
-Missing input or output delay  
-An output delay is missing on leds[5] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#67 Warning
-Missing input or output delay  
-An output delay is missing on leds[6] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#68 Warning
-Missing input or output delay  
-An output delay is missing on leds[7] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#69 Warning
-Missing input or output delay  
-An output delay is missing on leds[8] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#70 Warning
-Missing input or output delay  
-An output delay is missing on leds[9] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#71 Warning
-Missing input or output delay  
-An output delay is missing on video_de relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#72 Warning
-Missing input or output delay  
-An output delay is missing on video_hsync relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#73 Warning
-Missing input or output delay  
-An output delay is missing on video_red[0] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#74 Warning
-Missing input or output delay  
-An output delay is missing on video_red[1] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#75 Warning
-Missing input or output delay  
-An output delay is missing on video_red[2] relative to clock(s) clk
-Related violations: <none>
-
-TIMING-18#76 Warning
-Missing input or output delay  
-An output delay is missing on video_vsync relative to clock(s) clk
-Related violations: <none>
-
-TIMING-47#1 Warning
-False path or asynchronous clock group between synchronous clocks  
-A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
-Related violations: <none>
-
-TIMING-47#2 Warning
-False path or asynchronous clock group between synchronous clocks  
-A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
-Related violations: <none>
-
-XDCC-1#1 Warning
-Scoped Clock constraint overwritten with the same name  
-A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
-New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
-Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
-Related violations: <none>
-
-XDCC-7#1 Warning
-Scoped Clock constraint overwritten on the same source  
-A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
-New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
-Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
-Related violations: <none>
-
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/power.rpt

@@ -1,180 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
-| Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date             : Wed Jul  8 03:34:25 2026
-| Host             : fedora running 64-bit unknown
-| Command          : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt
-| Design           : soc_top
-| Device           : xc7a200tfbg676-1
-| Design State     : routed
-| Grade            : commercial
-| Process          : typical
-| Characterization : Production
-------------------------------------------------------------------------------------------------
-
-Power Report
-
-Table of Contents
------------------
-1. Summary
-1.1 On-Chip Components
-1.2 Power Supply Summary
-1.3 Confidence Level
-2. Settings
-2.1 Environment
-2.2 Clock Constraints
-3. Detailed Reports
-3.1 By Hierarchy
-
-1. Summary
-----------
-
-+--------------------------+--------------+
-| Total On-Chip Power (W)  | 0.549        |
-| Design Power Budget (W)  | Unspecified* |
-| Power Budget Margin (W)  | NA           |
-| Dynamic (W)              | 0.409        |
-| Device Static (W)        | 0.141        |
-| Effective TJA (C/W)      | 1.9          |
-| Max Ambient (C)          | 84.0         |
-| Junction Temperature (C) | 26.0         |
-| Confidence Level         | Low          |
-| Setting File             | ---          |
-| Simulation Activity File | ---          |
-| Design Nets Matched      | NA           |
-+--------------------------+--------------+
-* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
-
-
-1.1 On-Chip Components
-----------------------
-
-+--------------------------+-----------+----------+-----------+-----------------+
-| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
-+--------------------------+-----------+----------+-----------+-----------------+
-| Clocks                   |     0.042 |        7 |       --- |             --- |
-| Slice Logic              |     0.069 |   120086 |       --- |             --- |
-|   LUT as Logic           |     0.064 |    63754 |    133800 |           47.65 |
-|   CARRY4                 |     0.002 |     2859 |     33450 |            8.55 |
-|   LUT as Distributed RAM |    <0.001 |      740 |     46200 |            1.60 |
-|   Register               |    <0.001 |    39931 |    267600 |           14.92 |
-|   LUT as Shift Register  |    <0.001 |     1175 |     46200 |            2.54 |
-|   F7/F8 Muxes            |    <0.001 |     6036 |    133800 |            4.51 |
-|   Others                 |     0.000 |      318 |       --- |             --- |
-| Signals                  |     0.115 |    85084 |       --- |             --- |
-| Block RAM                |     0.019 |     23.5 |       365 |            6.44 |
-| PLL                      |     0.132 |        1 |        10 |           10.00 |
-| DSPs                     |     0.009 |       16 |       740 |            2.16 |
-| I/O                      |     0.023 |      202 |       400 |           50.50 |
-| Static Power             |     0.141 |          |           |                 |
-| Total                    |     0.549 |          |           |                 |
-+--------------------------+-----------+----------+-----------+-----------------+
-
-
-1.2 Power Supply Summary
-------------------------
-
-+-----------+-------------+-----------+-------------+------------+
-| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
-+-----------+-------------+-----------+-------------+------------+
-| Vccint    |       1.000 |     0.294 |       0.262 |      0.032 |
-| Vccaux    |       1.800 |     0.099 |       0.069 |      0.031 |
-| Vcco33    |       3.300 |     0.011 |       0.006 |      0.005 |
-| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
-| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
-| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
-| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
-| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
-| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
-| Vccbram   |       1.000 |     0.003 |       0.001 |      0.001 |
-| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
-| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
-| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
-+-----------+-------------+-----------+-------------+------------+
-
-
-1.3 Confidence Level
---------------------
-
-+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
-| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
-+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
-| Design implementation state | High       | Design is routed                                       |                                                                                                            |
-| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
-| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
-| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
-| Device models               | High       | Device models are Production                           |                                                                                                            |
-|                             |            |                                                        |                                                                                                            |
-| Overall confidence level    | Low        |                                                        |                                                                                                            |
-+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
-
-
-2. Settings
------------
-
-2.1 Environment
----------------
-
-+-----------------------+--------------------------+
-| Ambient Temp (C)      | 25.0                     |
-| ThetaJA (C/W)         | 1.9                      |
-| Airflow (LFM)         | 250                      |
-| Heat Sink             | medium (Medium Profile)  |
-| ThetaSA (C/W)         | 3.4                      |
-| Board Selection       | medium (10"x10")         |
-| # of Board Layers     | 12to15 (12 to 15 Layers) |
-| Board Temperature (C) | 25.0                     |
-+-----------------------+--------------------------+
-
-
-2.2 Clock Constraints
----------------------
-
-+-------------------+------------------------------------------+-----------------+
-| Clock             | Domain                                   | Constraint (ns) |
-+-------------------+------------------------------------------+-----------------+
-| clk               | clk                                      |            20.0 |
-| clkfbout_clk_pll  | pll_clk.u_clk_pll/inst/clkfbout_clk_pll  |            20.0 |
-| cpu_clk           | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll   |            30.3 |
-| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll |            40.0 |
-| sys_clk           | pll_clk.u_clk_pll/inst/sys_clk_clk_pll   |            20.0 |
-+-------------------+------------------------------------------+-----------------+
-
-
-3. Detailed Reports
--------------------
-
-3.1 By Hierarchy
-----------------
-
-+----------------------------+-----------+
-| Name                       | Power (W) |
-+----------------------------+-----------+
-| soc_top                    |     0.409 |
-|   pll_clk.u_clk_pll        |     0.133 |
-|     inst                   |     0.133 |
-|   u_Axi_CDC                |     0.002 |
-|   u_axi_uart_controller    |     0.001 |
-|     uart0                  |     0.001 |
-|       regs                 |     0.001 |
-|   u_cdma_matmul_bridge     |     0.001 |
-|   u_cpu                    |     0.018 |
-|     addr_trans             |     0.002 |
-|       tlb_entry            |     0.002 |
-|     btb                    |     0.002 |
-|     dcache                 |     0.004 |
-|     icache                 |     0.005 |
-|     u_csr                  |     0.002 |
-|   u_fft_mlkem_axi_slave    |     0.148 |
-|     u_fft_controller       |     0.032 |
-|       u_FFT                |     0.029 |
-|     u_mlkem_axi_cdc        |     0.002 |
-|     u_mlkem_axi_slave      |     0.115 |
-|       u_mlkem              |     0.113 |
-|   u_matmul_axi_slave       |     0.065 |
-|   u_snix_axil_cdma_mux_8ch |     0.009 |
-|     u_core_engine          |     0.004 |
-|       axis_fifo_u0         |     0.003 |
-+----------------------------+-----------+
-
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/route_status.rpt

@@ -1,12 +0,0 @@
-Design Route Status
-                                               :      # nets :
-   ------------------------------------------- : ----------- :
-   # of logical nets.......................... :      128919 :
-       # of nets not needing routing.......... :       43824 :
-           # of internally routed nets........ :       43359 :
-           # of nets with no loads............ :         465 :
-       # of routable nets..................... :       85095 :
-           # of fully routed nets............. :       85095 :
-       # of nets with routing errors.......... :           0 :
-   ------------------------------------------- : ----------- :
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization.rpt

@@ -1,237 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:05 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt
-| Design       : soc_top
-| Device       : 7a200tfbg676-1
-| Design State : Routed
-------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Slice Logic
-1.1 Summary of Registers by Type
-2. Slice Logic Distribution
-3. Memory
-4. DSP
-5. IO and GT Specific
-6. Clocking
-7. Specific Feature
-8. Primitives
-9. Black Boxes
-10. Instantiated Netlists
-
-1. Slice Logic
---------------
-
-+----------------------------+-------+-------+-----------+-------+
-|          Site Type         |  Used | Fixed | Available | Util% |
-+----------------------------+-------+-------+-----------+-------+
-| Slice LUTs                 | 60995 |     0 |    133800 | 45.59 |
-|   LUT as Logic             | 59140 |     0 |    133800 | 44.20 |
-|   LUT as Memory            |  1855 |     0 |     46200 |  4.02 |
-|     LUT as Distributed RAM |   740 |     0 |           |       |
-|     LUT as Shift Register  |  1115 |     0 |           |       |
-| Slice Registers            | 39931 |     0 |    267600 | 14.92 |
-|   Register as Flip Flop    | 39931 |     0 |    267600 | 14.92 |
-|   Register as Latch        |     0 |     0 |    267600 |  0.00 |
-| F7 Muxes                   |  4480 |     0 |     66900 |  6.70 |
-| F8 Muxes                   |  1556 |     0 |     33450 |  4.65 |
-+----------------------------+-------+-------+-----------+-------+
-
-
-1.1 Summary of Registers by Type
---------------------------------
-
-+-------+--------------+-------------+--------------+
-| Total | Clock Enable | Synchronous | Asynchronous |
-+-------+--------------+-------------+--------------+
-| 0     |            _ |           - |            - |
-| 0     |            _ |           - |          Set |
-| 0     |            _ |           - |        Reset |
-| 0     |            _ |         Set |            - |
-| 0     |            _ |       Reset |            - |
-| 0     |          Yes |           - |            - |
-| 24    |          Yes |           - |          Set |
-| 26637 |          Yes |           - |        Reset |
-| 139   |          Yes |         Set |            - |
-| 13131 |          Yes |       Reset |            - |
-+-------+--------------+-------------+--------------+
-
-
-2. Slice Logic Distribution
----------------------------
-
-+--------------------------------------------+-------+-------+-----------+-------+
-|                  Site Type                 |  Used | Fixed | Available | Util% |
-+--------------------------------------------+-------+-------+-----------+-------+
-| Slice                                      | 20066 |     0 |     33450 | 59.99 |
-|   SLICEL                                   | 13210 |     0 |           |       |
-|   SLICEM                                   |  6856 |     0 |           |       |
-| LUT as Logic                               | 59140 |     0 |    133800 | 44.20 |
-|   using O5 output only                     |     2 |       |           |       |
-|   using O6 output only                     | 49931 |       |           |       |
-|   using O5 and O6                          |  9207 |       |           |       |
-| LUT as Memory                              |  1855 |     0 |     46200 |  4.02 |
-|   LUT as Distributed RAM                   |   740 |     0 |           |       |
-|     using O5 output only                   |     0 |       |           |       |
-|     using O6 output only                   |    60 |       |           |       |
-|     using O5 and O6                        |   680 |       |           |       |
-|   LUT as Shift Register                    |  1115 |     0 |           |       |
-|     using O5 output only                   |    47 |       |           |       |
-|     using O6 output only                   |  1008 |       |           |       |
-|     using O5 and O6                        |    60 |       |           |       |
-| Slice Registers                            | 39931 |     0 |    267600 | 14.92 |
-|   Register driven from within the Slice    | 20433 |       |           |       |
-|   Register driven from outside the Slice   | 19498 |       |           |       |
-|     LUT in front of the register is unused | 10788 |       |           |       |
-|     LUT in front of the register is used   |  8710 |       |           |       |
-| Unique Control Sets                        |  1304 |       |     33450 |  3.90 |
-+--------------------------------------------+-------+-------+-----------+-------+
-* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
-
-
-3. Memory
----------
-
-+-------------------+------+-------+-----------+-------+
-|     Site Type     | Used | Fixed | Available | Util% |
-+-------------------+------+-------+-----------+-------+
-| Block RAM Tile    | 23.5 |     0 |       365 |  6.44 |
-|   RAMB36/FIFO*    |    8 |     0 |       365 |  2.19 |
-|     RAMB36E1 only |    8 |       |           |       |
-|   RAMB18          |   31 |     0 |       730 |  4.25 |
-|     RAMB18E1 only |   31 |       |           |       |
-+-------------------+------+-------+-----------+-------+
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
-4. DSP
-------
-
-+----------------+------+-------+-----------+-------+
-|    Site Type   | Used | Fixed | Available | Util% |
-+----------------+------+-------+-----------+-------+
-| DSPs           |   16 |     0 |       740 |  2.16 |
-|   DSP48E1 only |   16 |       |           |       |
-+----------------+------+-------+-----------+-------+
-
-
-5. IO and GT Specific
----------------------
-
-+-----------------------------+------+-------+-----------+-------+
-|          Site Type          | Used | Fixed | Available | Util% |
-+-----------------------------+------+-------+-----------+-------+
-| Bonded IOB                  |  202 |   202 |       400 | 50.50 |
-|   IOB Master Pads           |   97 |       |           |       |
-|   IOB Slave Pads            |  102 |       |           |       |
-| Bonded IPADs                |    0 |     0 |        26 |  0.00 |
-| Bonded OPADs                |    0 |     0 |        16 |  0.00 |
-| PHY_CONTROL                 |    0 |     0 |        10 |  0.00 |
-| PHASER_REF                  |    0 |     0 |        10 |  0.00 |
-| OUT_FIFO                    |    0 |     0 |        40 |  0.00 |
-| IN_FIFO                     |    0 |     0 |        40 |  0.00 |
-| IDELAYCTRL                  |    0 |     0 |        10 |  0.00 |
-| IBUFDS                      |    0 |     0 |       384 |  0.00 |
-| GTPE2_CHANNEL               |    0 |     0 |         8 |  0.00 |
-| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        40 |  0.00 |
-| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        40 |  0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       500 |  0.00 |
-| IBUFDS_GTE2                 |    0 |     0 |         4 |  0.00 |
-| ILOGIC                      |    0 |     0 |       400 |  0.00 |
-| OLOGIC                      |    0 |     0 |       400 |  0.00 |
-+-----------------------------+------+-------+-----------+-------+
-
-
-6. Clocking
------------
-
-+------------+------+-------+-----------+-------+
-|  Site Type | Used | Fixed | Available | Util% |
-+------------+------+-------+-----------+-------+
-| BUFGCTRL   |    4 |     0 |        32 | 12.50 |
-| BUFIO      |    0 |     0 |        40 |  0.00 |
-| MMCME2_ADV |    0 |     0 |        10 |  0.00 |
-| PLLE2_ADV  |    1 |     0 |        10 | 10.00 |
-| BUFMRCE    |    0 |     0 |        20 |  0.00 |
-| BUFHCE     |    0 |     0 |       120 |  0.00 |
-| BUFR       |    0 |     0 |        40 |  0.00 |
-+------------+------+-------+-----------+-------+
-
-
-7. Specific Feature
--------------------
-
-+-------------+------+-------+-----------+-------+
-|  Site Type  | Used | Fixed | Available | Util% |
-+-------------+------+-------+-----------+-------+
-| BSCANE2     |    0 |     0 |         4 |  0.00 |
-| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
-| DNA_PORT    |    0 |     0 |         1 |  0.00 |
-| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
-| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
-| ICAPE2      |    0 |     0 |         2 |  0.00 |
-| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
-| STARTUPE2   |    0 |     0 |         1 |  0.00 |
-| XADC        |    0 |     0 |         1 |  0.00 |
-+-------------+------+-------+-----------+-------+
-
-
-8. Primitives
--------------
-
-+-----------+-------+---------------------+
-|  Ref Name |  Used | Functional Category |
-+-----------+-------+---------------------+
-| LUT6      | 35413 |                 LUT |
-| FDCE      | 26637 |        Flop & Latch |
-| FDRE      | 13131 |        Flop & Latch |
-| LUT3      |  9384 |                 LUT |
-| LUT5      |  8477 |                 LUT |
-| LUT4      |  7294 |                 LUT |
-| LUT2      |  6978 |                 LUT |
-| MUXF7     |  4480 |               MuxFx |
-| CARRY4    |  2859 |          CarryLogic |
-| MUXF8     |  1556 |               MuxFx |
-| RAMD32    |  1060 |  Distributed Memory |
-| SRLC32E   |   992 |  Distributed Memory |
-| LUT1      |   801 |                 LUT |
-| RAMS32    |   328 |  Distributed Memory |
-| SRL16E    |   183 |  Distributed Memory |
-| FDSE      |   139 |        Flop & Latch |
-| IBUF      |   104 |                  IO |
-| OBUF      |    98 |                  IO |
-| OBUFT     |    66 |                  IO |
-| RAMD64E   |    32 |  Distributed Memory |
-| RAMB18E1  |    31 |        Block Memory |
-| FDPE      |    24 |        Flop & Latch |
-| DSP48E1   |    16 |    Block Arithmetic |
-| RAMB36E1  |     8 |        Block Memory |
-| BUFG      |     4 |               Clock |
-| PLLE2_ADV |     1 |               Clock |
-+-----------+-------+---------------------+
-
-
-9. Black Boxes
---------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
-10. Instantiated Netlists
--------------------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-| clk_pll  |    1 |
-+----------+------+
-
-

fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization_hier.rpt

@@ -1,276 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-| Date         : Wed Jul  8 03:34:06 2026
-| Host         : fedora running 64-bit unknown
-| Command      : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt
-| Design       : soc_top
-| Device       : 7a200tfbg676-1
-| Design State : Routed
--------------------------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Utilization by Hierarchy
-
-1. Utilization by Hierarchy
----------------------------
-
-+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
-|                 Instance                 |            Module            | Total LUTs | Logic LUTs | LUTRAMs | SRLs |  FFs  | RAMB36 | RAMB18 | DSP48 Blocks |
-+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
-| soc_top                                  |                        (top) |      60995 |      59140 |     740 | 1115 | 39931 |      8 |     31 |           16 |
-|   (soc_top)                              |                        (top) |        878 |        822 |      56 |    0 |     4 |      0 |      0 |            0 |
-|   pll_clk.u_clk_pll                      |                      clk_pll |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
-|     inst                                 |     clk_pll__clk_pll_clk_wiz |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
-|   pll_clk.u_rst_cpu                      |                     rst_sync |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|   pll_clk.u_rst_mlkem                    |                   rst_sync_0 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|   pll_clk.u_rst_sys                      |                   rst_sync_1 |          2 |          2 |       0 |    0 |     2 |      0 |      0 |            0 |
-|   u_AxiCrossbar_2x8                      |              AxiCrossbar_2x8 |        459 |        459 |       0 |    0 |   151 |      0 |      0 |            0 |
-|     (u_AxiCrossbar_2x8)                  |              AxiCrossbar_2x8 |          6 |          6 |       0 |    0 |    24 |      0 |      0 |            0 |
-|     axi4ReadOnlyArbiter_4                |          Axi4ReadOnlyArbiter |         18 |         18 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_82 |         18 |         18 |       0 |    0 |     3 |      0 |      0 |            0 |
-|     axi4ReadOnlyArbiter_5                |       Axi4ReadOnlyArbiter_65 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_81 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
-|     axi4ReadOnlyArbiter_6                |       Axi4ReadOnlyArbiter_66 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_80 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
-|     axi4ReadOnlyArbiter_7                |       Axi4ReadOnlyArbiter_67 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_79 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
-|     axi4WriteOnlyArbiter_4               |         Axi4WriteOnlyArbiter |         33 |         33 |       0 |    0 |    11 |      0 |      0 |            0 |
-|       (axi4WriteOnlyArbiter_4)           |         Axi4WriteOnlyArbiter |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_76 |         27 |         27 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_77 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         fifo                             |              StreamFifo_3_78 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     axi4WriteOnlyArbiter_5               |       Axi4WriteOnlyArbiter_1 |         15 |         15 |       0 |    0 |     9 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_73 |          7 |          7 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_74 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         fifo                             |              StreamFifo_3_75 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     axi4WriteOnlyArbiter_6               |       Axi4WriteOnlyArbiter_2 |         29 |         29 |       0 |    0 |    11 |      0 |      0 |            0 |
-|       (axi4WriteOnlyArbiter_6)           |       Axi4WriteOnlyArbiter_2 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       cmdArbiter                         |           StreamArbiter_7_70 |         20 |         20 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_71 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         fifo                             |              StreamFifo_3_72 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     axi4WriteOnlyArbiter_7               |       Axi4WriteOnlyArbiter_3 |         23 |         23 |       0 |    0 |    11 |      0 |      0 |            0 |
-|       (axi4WriteOnlyArbiter_7)           |       Axi4WriteOnlyArbiter_3 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       cmdArbiter                         |              StreamArbiter_7 |         15 |         15 |       0 |    0 |     3 |      0 |      0 |            0 |
-|       cmdRouteFork_translated_fifo       |       StreamFifoLowLatency_3 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         fifo                             |                 StreamFifo_3 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     axiIn_0_readOnly_decoder             |          Axi4ReadOnlyDecoder |         96 |         96 |       0 |    0 |    25 |      0 |      0 |            0 |
-|       (axiIn_0_readOnly_decoder)         |          Axi4ReadOnlyDecoder |         75 |         75 |       0 |    0 |    12 |      0 |      0 |            0 |
-|       errorSlave                         |  Axi4ReadOnlyErrorSlave_1_69 |         21 |         21 |       0 |    0 |    13 |      0 |      0 |            0 |
-|     axiIn_0_writeOnly_decoder            |         Axi4WriteOnlyDecoder |         40 |         40 |       0 |    0 |    18 |      0 |      0 |            0 |
-|       (axiIn_0_writeOnly_decoder)        |         Axi4WriteOnlyDecoder |         20 |         20 |       0 |    0 |    16 |      0 |      0 |            0 |
-|       errorSlave                         | Axi4WriteOnlyErrorSlave_1_68 |         21 |         21 |       0 |    0 |     2 |      0 |      0 |            0 |
-|     axiIn_1_readOnly_decoder             |        Axi4ReadOnlyDecoder_1 |        133 |        133 |       0 |    0 |    17 |      0 |      0 |            0 |
-|       (axiIn_1_readOnly_decoder)         |        Axi4ReadOnlyDecoder_1 |        118 |        118 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       errorSlave                         |     Axi4ReadOnlyErrorSlave_1 |         15 |         15 |       0 |    0 |     9 |      0 |      0 |            0 |
-|     axiIn_1_writeOnly_decoder            |       Axi4WriteOnlyDecoder_1 |         30 |         30 |       0 |    0 |    14 |      0 |      0 |            0 |
-|       (axiIn_1_writeOnly_decoder)        |       Axi4WriteOnlyDecoder_1 |         18 |         18 |       0 |    0 |    12 |      0 |      0 |            0 |
-|       errorSlave                         |    Axi4WriteOnlyErrorSlave_1 |         12 |         12 |       0 |    0 |     2 |      0 |      0 |            0 |
-|   u_Axi_CDC                              |                      Axi_CDC |        410 |        282 |     128 |    0 |   317 |      0 |      0 |            0 |
-|     arFifo                               |            StreamFifoCC_3_48 |        181 |        145 |      36 |    0 |    77 |      0 |      0 |            0 |
-|       (arFifo)                           |            StreamFifoCC_3_48 |        176 |        140 |      36 |    0 |    65 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                BufferCC_9_63 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |               BufferCC_11_64 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     awFifo                               |              StreamFifoCC_49 |        103 |         67 |      36 |    0 |    79 |      0 |      0 |            0 |
-|       (awFifo)                           |              StreamFifoCC_49 |         99 |         63 |      36 |    0 |    65 |      0 |      0 |            0 |
-|       bufferCC_12                        |               BufferCC_10_60 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                BufferCC_9_61 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |               BufferCC_11_62 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     bFifo                                |            StreamFifoCC_2_50 |         15 |         15 |       0 |    0 |    26 |      0 |      0 |            0 |
-|       (bFifo)                            |            StreamFifoCC_2_50 |          8 |          8 |       0 |    0 |    12 |      0 |      0 |            0 |
-|       bufferCC_12                        |                BufferCC_5_57 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                BufferCC_4_58 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |                BufferCC_6_59 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     rFifo                                |            StreamFifoCC_4_51 |         45 |         17 |      28 |    0 |    66 |      0 |      0 |            0 |
-|       (rFifo)                            |            StreamFifoCC_4_51 |         41 |         13 |      28 |    0 |    50 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                  BufferCC_55 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |                BufferCC_1_56 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
-|     wFifo                                |            StreamFifoCC_1_52 |         66 |         38 |      28 |    0 |    69 |      0 |      0 |            0 |
-|       (wFifo)                            |            StreamFifoCC_1_52 |         62 |         34 |      28 |    0 |    53 |      0 |      0 |            0 |
-|       popToPushGray_buffercc             |                BufferCC_7_53 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       pushToPopGray_buffercc             |                BufferCC_8_54 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
-|   u_axi_axil_adapter                     |             axi_axil_adapter |       1073 |       1073 |       0 |    0 |   173 |      0 |      0 |            0 |
-|     axi_axil_adapter_rd_inst             |          axi_axil_adapter_rd |        498 |        498 |       0 |    0 |    85 |      0 |      0 |            0 |
-|     axi_axil_adapter_wr_inst             |          axi_axil_adapter_wr |        575 |        575 |       0 |    0 |    88 |      0 |      0 |            0 |
-|   u_axi_dvi                              |                      axi_dvi |        283 |        283 |       0 |    0 |   211 |      0 |      0 |            0 |
-|   u_axi_ram                              |     axi_wrap_ram_sp_external |        350 |        350 |       0 |    0 |    78 |      0 |      0 |            0 |
-|     u_axi_sram_sp                        |         axi2sram_sp_external |        350 |        350 |       0 |    0 |    78 |      0 |      0 |            0 |
-|   u_axi_uart_controller                  |          axi_uart_controller |        683 |        667 |      16 |    0 |   457 |      0 |      0 |            0 |
-|     AA_axi2apb_bridge_cpu                |               axi2apb_bridge |        251 |        251 |       0 |    0 |   120 |      0 |      0 |            0 |
-|     uart0                                |                     UART_TOP |        432 |        416 |      16 |    0 |   337 |      0 |      0 |            0 |
-|       regs                               |                    uart_regs |        432 |        416 |      16 |    0 |   337 |      0 |      0 |            0 |
-|         (regs)                           |                    uart_regs |        119 |        119 |       0 |    0 |   155 |      0 |      0 |            0 |
-|         i_uart_sync_flops                |              uart_sync_flops |          3 |          3 |       0 |    0 |     2 |      0 |      0 |            0 |
-|         receiver                         |                uart_receiver |        229 |        221 |       8 |    0 |   124 |      0 |      0 |            0 |
-|           (receiver)                     |                uart_receiver |         68 |         68 |       0 |    0 |    54 |      0 |      0 |            0 |
-|           fifo_rx                        |                   uart_rfifo |        161 |        153 |       8 |    0 |    70 |      0 |      0 |            0 |
-|             (fifo_rx)                    |                   uart_rfifo |        143 |        143 |       0 |    0 |    62 |      0 |      0 |            0 |
-|             rfifo                        |                   raminfr_47 |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
-|         transmitter                      |             uart_transmitter |         83 |         75 |       8 |    0 |    56 |      0 |      0 |            0 |
-|           (transmitter)                  |             uart_transmitter |         41 |         41 |       0 |    0 |    35 |      0 |      0 |            0 |
-|           fifo_tx                        |                   uart_tfifo |         43 |         35 |       8 |    0 |    21 |      0 |      0 |            0 |
-|             (fifo_tx)                    |                   uart_tfifo |         24 |         24 |       0 |    0 |    13 |      0 |      0 |            0 |
-|             tfifo                        |                      raminfr |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
-|   u_cdma_matmul_bridge                   |           cdma_matmul_bridge |        251 |        251 |       0 |    0 |   578 |      0 |      0 |            0 |
-|   u_confreg                              |                      confreg |        390 |        390 |       0 |    0 |   476 |      0 |      0 |            0 |
-|     (u_confreg)                          |                      confreg |        230 |        230 |       0 |    0 |   399 |      0 |      0 |            0 |
-|     u_digitaltube_controller             |       digitaltube_controller |         16 |         16 |       0 |    0 |    24 |      0 |      0 |            0 |
-|     u_int_ctrl                           |                     int_ctrl |        144 |        144 |       0 |    0 |    53 |      0 |      0 |            0 |
-|   u_cpu                                  |                     core_top |       8551 |       8299 |     252 |    0 |  5591 |      0 |     20 |            0 |
-|     (u_cpu)                              |                     core_top |        519 |        519 |       0 |    0 |     1 |      0 |      0 |            0 |
-|     addr_trans                           |                   addr_trans |       2247 |       2107 |     140 |    0 |  1244 |      0 |      0 |            0 |
-|       (addr_trans)                       |                   addr_trans |          0 |          0 |       0 |    0 |    40 |      0 |      0 |            0 |
-|       tlb_entry                          |                    tlb_entry |       2247 |       2107 |     140 |    0 |  1204 |      0 |      0 |            0 |
-|     axi_bridge                           |                   axi_bridge |         40 |         40 |       0 |    0 |   214 |      0 |      0 |            0 |
-|     btb                                  |                          btb |       1046 |        966 |      80 |    0 |  1611 |      0 |      0 |            0 |
-|       (btb)                              |                          btb |       1044 |        964 |      80 |    0 |  1611 |      0 |      0 |            0 |
-|       dec_btb_add_entry                  |                 decoder_5_32 |          3 |          3 |       0 |    0 |     0 |      0 |      0 |            0 |
-|     dcache                               |                       dcache |        552 |        520 |      32 |    0 |   146 |      0 |     10 |            0 |
-|       (dcache)                           |                       dcache |         87 |         55 |      32 |    0 |   138 |      0 |      0 |            0 |
-|       data_ram_way[0].data_ram_bank[0].u |            data_bank_sram_36 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_37 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_38 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_39 |         51 |         51 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_40 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_41 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_42 |         81 |         81 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_43 |         54 |         54 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       lfsr                               |                      lfsr_44 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       tagv_ram_way[0].u                  |                 tagv_sram_45 |         62 |         62 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       tagv_ram_way[1].u                  |                 tagv_sram_46 |         41 |         41 |       0 |    0 |     0 |      0 |      1 |            0 |
-|     exe_stage                            |                    exe_stage |        663 |        663 |       0 |    0 |   233 |      0 |      0 |            0 |
-|       (exe_stage)                        |                    exe_stage |        632 |        632 |       0 |    0 |   233 |      0 |      0 |            0 |
-|       u_alu                              |                          alu |         33 |         33 |       0 |    0 |     0 |      0 |      0 |            0 |
-|     icache                               |                       icache |        235 |        235 |       0 |    0 |    55 |      0 |     10 |            0 |
-|       (icache)                           |                       icache |         12 |         12 |       0 |    0 |    47 |      0 |      0 |            0 |
-|       data_ram_way[0].data_ram_bank[0].u |               data_bank_sram |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_28 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_29 |         67 |         67 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_30 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_31 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_32 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_33 |         35 |         35 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_34 |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       lfsr                               |                         lfsr |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       tagv_ram_way[0].u                  |                    tagv_sram |         15 |         15 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       tagv_ram_way[1].u                  |                 tagv_sram_35 |         87 |         87 |       0 |    0 |     0 |      0 |      1 |            0 |
-|     id_stage                             |                     id_stage |       1054 |       1054 |       0 |    0 |   108 |      0 |      0 |            0 |
-|     if_stage                             |                     if_stage |        135 |        135 |       0 |    0 |   173 |      0 |      0 |            0 |
-|     mem_stage                            |                    mem_stage |        116 |        116 |       0 |    0 |   211 |      0 |      0 |            0 |
-|     u_csr                                |                          csr |        200 |        200 |       0 |    0 |   663 |      0 |      0 |            0 |
-|     u_div                                |                          div |        142 |        142 |       0 |    0 |   107 |      0 |      0 |            0 |
-|     u_mul                                |                          mul |        936 |        936 |       0 |    0 |   592 |      0 |      0 |            0 |
-|     wb_stage                             |                     wb_stage |        680 |        680 |       0 |    0 |   233 |      0 |      0 |            0 |
-|   u_fft_mlkem_axi_slave                  |          fft_mlkem_axi_slave |      36148 |      34927 |     112 | 1109 | 27165 |      8 |     10 |           16 |
-|     (u_fft_mlkem_axi_slave)              |          fft_mlkem_axi_slave |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
-|     u_fft_controller                     |               fft_controller |       2646 |       1606 |       0 | 1040 |  1083 |      6 |      4 |           16 |
-|       (u_fft_controller)                 |               fft_controller |        123 |        123 |       0 |    0 |   100 |      0 |      0 |            0 |
-|       u_FFT                              |                          FFT |       2496 |       1456 |       0 | 1040 |   983 |      6 |      0 |           16 |
-|         SU1                              |                      SdfUnit |       1071 |        303 |       0 |  768 |   197 |      2 |      0 |            4 |
-|           (SU1)                          |                      SdfUnit |        205 |        205 |       0 |    0 |   133 |      0 |      0 |            0 |
-|           BF1                            |                 Butterfly_24 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            | Butterfly__parameterized0_25 |         33 |         33 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           DB1                            |                  DelayBuffer |        562 |         50 |       0 |  512 |    32 |      0 |      0 |            0 |
-|           DB2                            |  DelayBuffer__parameterized0 |        256 |          0 |       0 |  256 |    32 |      0 |      0 |            0 |
-|           MU                             |                  Multiply_26 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            4 |
-|           TW                             |                   Twiddle_27 |          1 |          1 |       0 |    0 |     0 |      2 |      0 |            0 |
-|         SU2                              |      SdfUnit__parameterized0 |        492 |        300 |       0 |  192 |   197 |      2 |      0 |            4 |
-|           (SU2)                          |      SdfUnit__parameterized0 |         73 |         73 |       0 |    0 |   133 |      0 |      0 |            0 |
-|           BF1                            |                 Butterfly_20 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            | Butterfly__parameterized0_21 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           DB1                            |  DelayBuffer__parameterized1 |        240 |        112 |       0 |  128 |    32 |      0 |      0 |            0 |
-|           DB2                            |  DelayBuffer__parameterized2 |        128 |         64 |       0 |   64 |    32 |      0 |      0 |            0 |
-|           MU                             |                  Multiply_22 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
-|           TW                             |                   Twiddle_23 |          3 |          3 |       0 |    0 |     0 |      2 |      0 |            0 |
-|         SU3                              |      SdfUnit__parameterized1 |        346 |        298 |       0 |   48 |   197 |      0 |      0 |            4 |
-|           (SU3)                          |      SdfUnit__parameterized1 |         74 |         74 |       0 |    0 |   133 |      0 |      0 |            0 |
-|           BF1                            |                 Butterfly_17 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            | Butterfly__parameterized0_18 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           DB1                            |  DelayBuffer__parameterized3 |        144 |        112 |       0 |   32 |    32 |      0 |      0 |            0 |
-|           DB2                            |  DelayBuffer__parameterized4 |         80 |         64 |       0 |   16 |    32 |      0 |      0 |            0 |
-|           MU                             |                  Multiply_19 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
-|         SU4                              |      SdfUnit__parameterized2 |        327 |        295 |       0 |   32 |   197 |      2 |      0 |            4 |
-|           (SU4)                          |      SdfUnit__parameterized2 |         69 |         69 |       0 |    0 |   133 |      0 |      0 |            0 |
-|           BF1                            |                 Butterfly_15 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            | Butterfly__parameterized0_16 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           DB1                            |  DelayBuffer__parameterized5 |        128 |        112 |       0 |   16 |    32 |      0 |      0 |            0 |
-|           DB2                            |  DelayBuffer__parameterized6 |         80 |         64 |       0 |   16 |    32 |      0 |      0 |            0 |
-|           MU                             |                     Multiply |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
-|           TW                             |                      Twiddle |          2 |          2 |       0 |    0 |     0 |      2 |      0 |            0 |
-|         SU5                              |      SdfUnit__parameterized3 |        260 |        260 |       0 |    0 |   195 |      0 |      0 |            0 |
-|           (SU5)                          |      SdfUnit__parameterized3 |         68 |         68 |       0 |    0 |    99 |      0 |      0 |            0 |
-|           BF1                            |                    Butterfly |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           BF2                            |    Butterfly__parameterized0 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
-|           DB1                            |  DelayBuffer__parameterized7 |        112 |        112 |       0 |    0 |    64 |      0 |      0 |            0 |
-|           DB2                            |  DelayBuffer__parameterized8 |         64 |         64 |       0 |    0 |    32 |      0 |      0 |            0 |
-|       u_in0                              |                     my_bram0 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       u_in1                              |                  my_bram0_12 |          2 |          2 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       u_out0                             |                  my_bram0_13 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
-|       u_out1                             |                  my_bram0_14 |         25 |         25 |       0 |    0 |     0 |      0 |      1 |            0 |
-|     u_mlkem_axi_cdc                      |                    Axi_CDC_5 |        421 |        309 |     112 |    0 |   272 |      0 |      0 |            0 |
-|       arFifo                             |               StreamFifoCC_3 |         53 |         25 |      28 |    0 |    55 |      0 |      0 |            0 |
-|         (arFifo)                         |               StreamFifoCC_3 |         44 |         16 |      28 |    0 |    43 |      0 |      0 |            0 |
-|         popToPushGray_buffercc           |                BufferCC_9_10 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         pushToPopGray_buffercc           |               BufferCC_11_11 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       awFifo                             |                 StreamFifoCC |         40 |         16 |      24 |    0 |    49 |      0 |      0 |            0 |
-|         (awFifo)                         |                 StreamFifoCC |         31 |          7 |      24 |    0 |    35 |      0 |      0 |            0 |
-|         bufferCC_12                      |                  BufferCC_10 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|         popToPushGray_buffercc           |                   BufferCC_9 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         pushToPopGray_buffercc           |                  BufferCC_11 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       bFifo                              |               StreamFifoCC_2 |         18 |         14 |       4 |    0 |    27 |      0 |      0 |            0 |
-|         (bFifo)                          |               StreamFifoCC_2 |         11 |          7 |       4 |    0 |    13 |      0 |      0 |            0 |
-|         bufferCC_12                      |                   BufferCC_5 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
-|         popToPushGray_buffercc           |                   BufferCC_4 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
-|         pushToPopGray_buffercc           |                   BufferCC_6 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
-|       rFifo                              |               StreamFifoCC_4 |         57 |         29 |      28 |    0 |    72 |      0 |      0 |            0 |
-|         (rFifo)                          |               StreamFifoCC_4 |         49 |         21 |      28 |    0 |    56 |      0 |      0 |            0 |
-|         popToPushGray_buffercc           |                     BufferCC |          4 |          4 |       0 |    0 |     8 |      0 |      0 |            0 |
-|         pushToPopGray_buffercc           |                   BufferCC_1 |          5 |          5 |       0 |    0 |     8 |      0 |      0 |            0 |
-|       wFifo                              |               StreamFifoCC_1 |        253 |        225 |      28 |    0 |    69 |      0 |      0 |            0 |
-|         (wFifo)                          |               StreamFifoCC_1 |        248 |        220 |      28 |    0 |    53 |      0 |      0 |            0 |
-|         popToPushGray_buffercc           |                   BufferCC_7 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
-|         pushToPopGray_buffercc           |                   BufferCC_8 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
-|     u_mlkem_axi_slave                    |              mlkem_axi_slave |      33082 |      33013 |       0 |   69 | 25804 |      2 |      6 |            0 |
-|       (u_mlkem_axi_slave)                |              mlkem_axi_slave |       1202 |       1202 |       0 |    0 |  1068 |      0 |      0 |            0 |
-|       u_mlkem                            |                    mlkem_top |      31884 |      31815 |       0 |   69 | 24736 |      2 |      6 |            0 |
-|         (u_mlkem)                        |                    mlkem_top |       2738 |       2738 |       0 |    0 |  4960 |      0 |      0 |            0 |
-|         u_bank_a                         |      sd_bram__parameterized0 |         50 |         50 |       0 |    0 |     0 |      1 |      1 |            0 |
-|         u_bank_se                        |      sd_bram__parameterized1 |         70 |         70 |       0 |    0 |     0 |      1 |      0 |            0 |
-|         u_bank_t                         |      sd_bram__parameterized2 |        654 |        654 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_c_in_bram                      |                      sd_bram |       1312 |       1312 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_cbd                            |       sample_cbd_sync_shared |       2741 |       2741 |       0 |    0 |  3186 |      0 |      0 |            0 |
-|         u_comp                           |             comp_decomp_sync |        467 |        466 |       0 |    1 |   323 |      0 |      0 |            0 |
-|         u_ct_bram                        |                    sd_bram_6 |         13 |         13 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_dkp_bram                       |                    sd_bram_7 |         82 |         82 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_ek_bram                        |                    sd_bram_8 |       2121 |       2121 |       0 |    0 |     0 |      0 |      1 |            0 |
-|         u_keccak                         |                  keccak_core |       5274 |       5274 |       0 |    0 |  1606 |      0 |      0 |            0 |
-|         u_ntt                            |                     ntt_core |       8625 |       8582 |       0 |   43 |  3861 |      0 |      0 |            0 |
-|           (u_ntt)                        |                     ntt_core |       6101 |       6085 |       0 |   16 |  3358 |      0 |      0 |            0 |
-|           u_bf                           |          butterfly_unit_pipe |       2260 |       2234 |       0 |   26 |   286 |      0 |      0 |            0 |
-|             (u_bf)                       |          butterfly_unit_pipe |         69 |         44 |       0 |   25 |    75 |      0 |      0 |            0 |
-|             u_barrett                    |           barrett_mul_pipe_9 |       2192 |       2191 |       0 |    1 |   211 |      0 |      0 |            0 |
-|           u_scl                          |             barrett_mul_pipe |        265 |        264 |       0 |    1 |   217 |      0 |      0 |            0 |
-|         u_pmul                           |                poly_mul_sync |       3881 |       3856 |       0 |   25 |  6743 |      0 |      0 |            0 |
-|           (u_pmul)                       |                poly_mul_sync |       2434 |       2434 |       0 |    0 |  6280 |      0 |      0 |            0 |
-|           u_bc                           |            basecase_mul_pipe |       1447 |       1422 |       0 |   25 |   463 |      0 |      0 |            0 |
-|         u_sha3                           |              sha3_top_shared |       1766 |       1766 |       0 |    0 |  2388 |      0 |      0 |            0 |
-|         u_snt                            |       sample_ntt_sync_shared |       2109 |       2109 |       0 |    0 |  1669 |      0 |      0 |            0 |
-|   u_matmul_axi_slave                     |             matmul_axi_slave |       9758 |       9576 |     176 |    6 |  3248 |      0 |      0 |            0 |
-|     (u_matmul_axi_slave)                 |             matmul_axi_slave |       5637 |       5455 |     176 |    6 |  2480 |      0 |      0 |            0 |
-|     mult_inst[0].u_mult                  |         pipelined_mult_32x32 |       1063 |       1063 |       0 |    0 |   192 |      0 |      0 |            0 |
-|     mult_inst[1].u_mult                  |       pipelined_mult_32x32_2 |        999 |        999 |       0 |    0 |   192 |      0 |      0 |            0 |
-|     mult_inst[2].u_mult                  |       pipelined_mult_32x32_3 |       1062 |       1062 |       0 |    0 |   192 |      0 |      0 |            0 |
-|     mult_inst[3].u_mult                  |       pipelined_mult_32x32_4 |        997 |        997 |       0 |    0 |   192 |      0 |      0 |            0 |
-|   u_snix_axil_cdma_mux_8ch               |           snix_axil_cdma_mux |       1788 |       1788 |       0 |    0 |  1476 |      0 |      1 |            0 |
-|     (u_snix_axil_cdma_mux_8ch)           |           snix_axil_cdma_mux |        751 |        751 |       0 |    0 |  1180 |      0 |      0 |            0 |
-|     u_core_engine                        |               snix_axi_mm2mm |       1038 |       1038 |       0 |    0 |   296 |      0 |      1 |            0 |
-|       (u_core_engine)                    |               snix_axi_mm2mm |        762 |        762 |       0 |    0 |   243 |      0 |      0 |            0 |
-|       axis_fifo_u0                       |               snix_axis_fifo |        276 |        276 |       0 |    0 |    53 |      0 |      1 |            0 |
-|         u_fifo                           |               snix_sync_fifo |        276 |        276 |       0 |    0 |    53 |      0 |      1 |            0 |
-+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
-* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
-
-

rtl/ip/PLL_2019_2/.gitignore

@@ -1 +0,0 @@
-PLL_*

rtl/ip/PLL_2019_2/clk_pll.xci

@@ -35,12 +35,6 @@
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.INSERT_VIP">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.PHASE">0.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_BUSIF"/>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_RESET"/>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.CLK_DOMAIN"/>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_HZ">100000000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.INSERT_VIP">0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
@@ -104,14 +98,14 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">32.97872</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">33.33333</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">50.00000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">32.97872</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">33.33333</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">33.000</spirit:configurableElementValue>
@@ -119,7 +113,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">50.00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">76.92308</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
@@ -136,13 +130,13 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">50.00000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">76.92308</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
@@ -210,7 +204,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.66</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.33</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.33</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.33</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.33</spirit:configurableElementValue>
@@ -252,20 +246,24 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">31.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">20.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">20.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">47.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">30.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">20</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">31</spirit:configurableElementValue>
+<<<<<<< Updated upstream
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+=======
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">13</spirit:configurableElementValue>
+>>>>>>> Stashed changes
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
@@ -295,17 +293,23 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+<<<<<<< Updated upstream
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__32.97872______0.000______50.0______130.093____123.600</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__50.00000______0.000______50.0______122.035____123.600</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">mlkem_clk__50.00000______0.000______50.0______122.035____123.600</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+=======
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__33.33333______0.000______50.0______215.691____164.985</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__50.00000______0.000______50.0______192.113____164.985</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">mlkem_clk__76.92308______0.000______50.0______172.249____164.985</spirit:configurableElementValue>
+>>>>>>> Stashed changes
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
@@ -438,14 +442,14 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">122.035</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">110.420</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">123.600</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
@@ -531,20 +535,24 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">20</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">20.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">47</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">30</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">20</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">31</spirit:configurableElementValue>
+<<<<<<< Updated upstream
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+=======
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">13</spirit:configurableElementValue>
+>>>>>>> Stashed changes
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
@@ -572,8 +580,13 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">3</spirit:configurableElementValue>
+<<<<<<< Updated upstream
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+=======
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">true</spirit:configurableElementValue>
+>>>>>>> Stashed changes
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
@@ -722,6 +735,9 @@
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT1_PORT" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT2_PORT" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT3_PORT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
@@ -731,6 +747,7 @@
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OVERRIDE_MMCM" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_PORT" xilinx:valueSource="user"/>

sdk/software/examples/mlkem_test/result.txt

@@ -0,0 +1,97 @@
+MLKEM_START
+MLKEM_INPUTS=STATIC_KAT_COUNT_0
+MLKEM_LEVELS=k2,k3,k4
+MLKEM_DIAG_MODE=isolated_sw_cpu_dma
+MLKEM_DIAG_ITERS=100
+
+============================================================
+ML-KEM-512 isolated diagnostic (k=2)
+EK=800 bytes, DK=1632 bytes, CT=768 bytes
+EXPECT_EK32=80b70100831d7ee168f47392483119f93863ecb0bc605312d35728876b00f5f5
+EXPECT_CT32=917e59d1e182a29648a61955a154b304a842f458eba593f3065fb7d744fba24f
+EXPECT_SS=2b5c52ee72946331983ba050be0f435055c0547901e03559b356517889ea27c5
+MLKEM512_SW_ONLY_BEGIN iters=100
+MLKEM512_SW_ONLY_ITERS=100
+MLKEM512_SW_ONLY_FAILS=0
+MLKEM512_SW_ONLY_AVG_CYCLES=2594034
+MLKEM512_SW_ONLY_AVG_US=78607
+MLKEM512_SW_ONLY_RESULT=PASS
+MLKEM512_SW_ONLY_END
+MLKEM512_CPU_ONLY_BEGIN iters=100
+MLKEM512_CPU_ONLY_ITERS=100
+MLKEM512_CPU_ONLY_FAILS=0
+MLKEM512_CPU_ONLY_AVG_CYCLES=200471
+MLKEM512_CPU_ONLY_AVG_US=6074
+MLKEM512_CPU_ONLY_RESULT=PASS
+MLKEM512_CPU_ONLY_END
+MLKEM512_DMA_ONLY_BEGIN iters=100
+MLKEM512_DMA_ONLY_ITERS=100
+MLKEM512_DMA_ONLY_FAILS=0
+MLKEM512_DMA_ONLY_AVG_CYCLES=52995
+MLKEM512_DMA_ONLY_AVG_US=1605
+MLKEM512_DMA_ONLY_RESULT=PASS
+MLKEM512_DMA_ONLY_END
+MLKEM512_ISOLATED_FAILS=0
+MLKEM512_RESULT=PASS
+
+============================================================
+ML-KEM-768 isolated diagnostic (k=3)
+EK=1184 bytes, DK=2400 bytes, CT=1088 bytes
+EXPECT_EK32=01f60af1dc8e6360ae78b59d4a5042eb9145a269046d6236b8304f305c2d9dcb
+EXPECT_CT32=16a61ff84787fd4a5f19ca59b3657db3a106a7329e2d62747a2ef85149163109
+EXPECT_SS=b408d5d115713f0a93047dbbea832e4340787686d59a9a2d106bd662ba0aa035
+MLKEM768_SW_ONLY_BEGIN iters=100
+MLKEM768_SW_ONLY_ITERS=100
+MLKEM768_SW_ONLY_FAILS=0
+MLKEM768_SW_ONLY_AVG_CYCLES=4065123
+MLKEM768_SW_ONLY_AVG_US=123185
+MLKEM768_SW_ONLY_RESULT=PASS
+MLKEM768_SW_ONLY_END
+MLKEM768_CPU_ONLY_BEGIN iters=100
+MLKEM768_CPU_ONLY_ITERS=100
+MLKEM768_CPU_ONLY_FAILS=0
+MLKEM768_CPU_ONLY_AVG_CYCLES=296193
+MLKEM768_CPU_ONLY_AVG_US=8975
+MLKEM768_CPU_ONLY_RESULT=PASS
+MLKEM768_CPU_ONLY_END
+MLKEM768_DMA_ONLY_BEGIN iters=100
+MLKEM768_DMA_ONLY_ITERS=100
+MLKEM768_DMA_ONLY_FAILS=0
+MLKEM768_DMA_ONLY_AVG_CYCLES=80648
+MLKEM768_DMA_ONLY_AVG_US=2443
+MLKEM768_DMA_ONLY_RESULT=PASS
+MLKEM768_DMA_ONLY_END
+MLKEM768_ISOLATED_FAILS=0
+MLKEM768_RESULT=PASS
+
+============================================================
+ML-KEM-1024 isolated diagnostic (k=4)
+EK=1568 bytes, DK=3168 bytes, CT=1568 bytes
+EXPECT_EK32=a8122f376b3f5d355263eba522c43995044beca78b9ba9924b87035490ae78a9
+EXPECT_CT32=707d18cabcf89670c80003b47d2b8678ad0da4aaad781a3351e82ac3e447e701
+EXPECT_SS=23f211b84a6ee20c8c29f6e5314c91b414e940513d380add17bd724ab3a13a52
+MLKEM1024_SW_ONLY_BEGIN iters=100
+MLKEM1024_SW_ONLY_ITERS=100
+MLKEM1024_SW_ONLY_FAILS=0
+MLKEM1024_SW_ONLY_AVG_CYCLES=6041204
+MLKEM1024_SW_ONLY_AVG_US=183066
+MLKEM1024_SW_ONLY_RESULT=PASS
+MLKEM1024_SW_ONLY_END
+MLKEM1024_CPU_ONLY_BEGIN iters=100
+MLKEM1024_CPU_ONLY_ITERS=100
+MLKEM1024_CPU_ONLY_FAILS=0
+MLKEM1024_CPU_ONLY_AVG_CYCLES=404476
+MLKEM1024_CPU_ONLY_AVG_US=12256
+MLKEM1024_CPU_ONLY_RESULT=PASS
+MLKEM1024_CPU_ONLY_END
+MLKEM1024_DMA_ONLY_BEGIN iters=100
+MLKEM1024_DMA_ONLY_ITERS=100
+MLKEM1024_DMA_ONLY_FAILS=0
+MLKEM1024_DMA_ONLY_AVG_CYCLES=113273
+MLKEM1024_DMA_ONLY_AVG_US=3432
+MLKEM1024_DMA_ONLY_RESULT=PASS
+MLKEM1024_DMA_ONLY_END
+MLKEM1024_ISOLATED_FAILS=0
+MLKEM1024_RESULT=PASS
+MLKEM_RESULT=PASS
+MLKEM_DONE