fallensigh/ciciec2026
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v0.1
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5 Commits

Author SHA1 Message Date
FallenSigh
69de12e79f update test data and remove mif files 2026-07-05 20:16:13 +08:00
FallenSigh
ca1472d859 Stop tracking generated binary images 2026-07-05 20:12:56 +08:00
FallenSigh
dd6053ab73 add test data 2026-06-26 21:36:55 +08:00
FallenSigh
20611157c3 tools: add extract_cbor_uart.py — extract UART output from CBOR trace files 
Parses CBOR hardware trace format, extracts UART serial output bytes,
and optionally parses MATMUL timing markers + pipeline diagnostics.

Usage:
  python3 tools/extract_cbor_uart.py <file.cbor>          # full UART output
  python3 tools/extract_cbor_uart.py <file.cbor> -s       # timing summary
  python3 tools/extract_cbor_uart.py <file.cbor> -o out   # save to file
 2026-06-26 17:40:20 +08:00
FallenSigh
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00