Commit Graph

5 Commits

Author SHA1 Message Date
7c60da78cb optimize 2026-07-13 07:10:30 +08:00
886ae8ad3f Sync fast SRAM read burst controller 2026-07-06 00:19:25 +08:00
297b93b828 优化sram的写路径,待验证 2026-07-02 00:36:59 +08:00
ed2876b3a8 Pipeline external SRAM reads 2026-07-02 00:23:57 +08:00
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00