5972facc0a
Pipeline matmul multiplier: 2-stage to fix WNS
...
Split compute into stage1 (compute → partial) and
stage2 (partial → c_data). Halves CARRY4 chain depth
from 16 to ~8 levels. Compute cycles: 16 → 32.
2026-06-24 21:40:34 +08:00
5ee2833a2b
Remove FFT module, tie off slave 6, fix linter issues
2026-06-24 20:54:33 +08:00
db2ad12dbb
Add verilator pragma to suppress BLKLOOPINIT in DelayBuffer.v
2026-06-24 20:41:52 +08:00
ff6e572996
matmul_test: rewrite for ExtRAM flow, add IP error debug
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- Rewrite main.c to read from ExtRAM (0x1c400000), compute
via matmul IP, write results back. Matches testbench
expectation of 10 groups.
- Add in matmul_axi_slave to trace error writes
2026-06-24 01:49:02 +08:00
fe8eff0aa0
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
fbc993b846
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
