acb158a392
Update matmul RTL, remove shift_add_mult.v
2026-06-25 00:47:43 +08:00
641d055f18
User mods: matmul RTL + shift_add_mult + C program
2026-06-25 00:43:16 +08:00
f05c445ef3
Sync matmul IP (burst support) from no-fft
2026-06-25 00:12:02 +08:00
5972facc0a
Pipeline matmul multiplier: 2-stage to fix WNS
...
Split compute into stage1 (compute → partial) and
stage2 (partial → c_data). Halves CARRY4 chain depth
from 16 to ~8 levels. Compute cycles: 16 → 32.
2026-06-24 21:40:34 +08:00
ff6e572996
matmul_test: rewrite for ExtRAM flow, add IP error debug
...
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
via matmul IP, write results back. Matches testbench
expectation of 10 groups.
- Add in matmul_axi_slave to trace error writes
2026-06-24 01:49:02 +08:00
fbc993b846
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
