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fallensigh/ciciec2026
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21 Commits 5 Branches 1 Tag
8ea98874a590154a618464605d009956beed705b
Commit Graph

9 Commits

Author SHA1 Message Date
FallenSigh
8ea98874a5 Inline CRC32 computation into main (bypass function call) 2026-06-24 22:52:08 +08:00
FallenSigh
d27e147652 Fix escaped quotes 2026-06-24 22:50:14 +08:00
FallenSigh
f6146bd467 Minimal debug: CRC32 self-test + group 0 rdback in one line 2026-06-24 22:49:06 +08:00
FallenSigh
e39a655861 Add CRC32 self-test debug output 2026-06-24 22:42:46 +08:00
FallenSigh
bbd3e3358b Fix extra brace in debug code 2026-06-24 22:38:18 +08:00
FallenSigh
3269e83d68 Debug: check ExtRAM write-back at start/mid/end of range 2026-06-24 22:36:29 +08:00
FallenSigh
4a67ca5c83 Add debug output for group 0 write-back and group 1 compute 2026-06-24 22:09:06 +08:00
FallenSigh
aaefb04737 Sync asm/ (user-sample.c + Makefile) from test branch
MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.
2026-06-24 17:01:45 +08:00
FallenSigh
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00
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