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49 Commits 5 Branches 1 Tag
8e86d8693e2cdc66061cb3a9d511ebd870cdca91
Commit Graph

7 Commits

Author SHA1 Message Date
FallenSigh
1e36883a7c Fix CRC32 table entry 187 2026-06-25 01:26:53 +08:00
FallenSigh
3962058592 Fix CRC32 table entry 187 again (0x5CB30A04 -> 0x5CB36A04) 2026-06-25 01:24:04 +08:00
FallenSigh
31c2b53583 CRC32 on-the-fly from c_buf (bypass GCC volatile ExtRAM bug) 2026-06-25 01:19:57 +08:00
FallenSigh
641d055f18 User mods: matmul RTL + shift_add_mult + C program 2026-06-25 00:43:16 +08:00
FallenSigh
4a67ca5c83 Add debug output for group 0 write-back and group 1 compute 2026-06-24 22:09:06 +08:00
FallenSigh
aaefb04737 Sync asm/ (user-sample.c + Makefile) from test branch
MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.
2026-06-24 17:01:45 +08:00
FallenSigh
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00
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