4 Commits

Author	SHA1	Message	Date
FallenSigh	99e6c884d7	chore: untrack auto-generated PLL files, add .gitignore	2026-06-30 02:10:29 +08:00
FallenSigh	542495cb52	fix: replace UNUSEDPARAM/UNUSEDSIGNAL with UNUSED for verilator lint ... Verilator does not recognize UNUSEDPARAM or UNUSEDSIGNAL. Correct suppression code is UNUSED.	2026-06-30 02:10:07 +08:00
FallenSigh	fe8eff0aa0	Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists	2026-06-23 01:33:56 +08:00
FallenSigh	fbc993b846	Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC	2026-06-23 01:22:45 +08:00