fallensigh/ciciec2026
Archived
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
116 Commits 5 Branches 1 Tag
7c60da78cbb289f7fdcea34fee197f95855bbdea
Commit Graph

53 Commits

Author SHA1 Message Date
FallenSigh
ff6e572996 matmul_test: rewrite for ExtRAM flow, add IP error debug 
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
  via matmul IP, write results back. Matches testbench
  expectation of 10 groups.
- Add  in matmul_axi_slave to trace error writes
 2026-06-24 01:49:02 +08:00
FallenSigh
fe8eff0aa0 Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists 2026-06-23 01:33:56 +08:00
FallenSigh
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00