Commit Graph

4 Commits

Author SHA1 Message Date
81c636fb56 perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle
user-sample.c v2 optimizations:
- Pre-fire DMA Ch0 load at loop tail to overlap fully with IP compute
- Inline wait_matmul_done/wait_dma_done to eliminate function call overhead
- Inline DMA register writes, skip redundant STATUS_BUSY_BIT check
- Replace g%2 with XOR bank toggle (bank ^= 1)
- Cache volatile pointers in locals (ch0, ch1, mat_status, mat_ctrl)

Makefile: bump -O2 to -O3
2026-06-26 03:39:32 +08:00
a42568f635 Clean production code: -O2, read CRC32 from ExtRAM, remove all debug 2026-06-24 23:42:35 +08:00
aaefb04737 Sync asm/ (user-sample.c + Makefile) from test branch
MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.
2026-06-24 17:01:45 +08:00
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00