4 Commits

Author	SHA1	Message	Date
FallenSigh	641d055f18	User mods: matmul RTL + shift_add_mult + C program	2026-06-25 00:43:16 +08:00
FallenSigh	4a67ca5c83	Add debug output for group 0 write-back and group 1 compute	2026-06-24 22:09:06 +08:00
FallenSigh	aaefb04737	Sync asm/ (user-sample.c + Makefile) from test branch ... MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.	2026-06-24 17:01:45 +08:00
FallenSigh	fbc993b846	Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC	2026-06-23 01:22:45 +08:00