86eab428a7
Use parenthesized pairwise addition to prevent synthesis truncation
2026-06-25 03:41:58 +08:00
fba86b01a8
Add in C_ACCUM to debug accumulation sum
2026-06-25 03:38:26 +08:00
4e409f870c
Register mult_p before accumulation to prevent synthesis glitches
2026-06-25 03:27:51 +08:00
d9d03b16c6
Fix: wait for ALL 4 multipliers to finish before accumulation
2026-06-25 03:07:49 +08:00
d3e1b5fda4
Add missing AXI4 ports: awlock/awcache/awprot/arlock/arcache/arprot
2026-06-25 00:53:28 +08:00
828612164a
Re-remove FFT module (leaked in from main merge)
2026-06-25 00:51:54 +08:00
acb158a392
Update matmul RTL, remove shift_add_mult.v
2026-06-25 00:47:43 +08:00
641d055f18
User mods: matmul RTL + shift_add_mult + C program
2026-06-25 00:43:16 +08:00
f05c445ef3
Sync matmul IP (burst support) from no-fft
2026-06-25 00:12:02 +08:00
d5ad070ca0
Restore FFT module on main branch
2026-06-25 00:10:42 +08:00
2edf058e97
Merge branch 'main' into no-fft
2026-06-24 21:41:50 +08:00
bbdc1fd7fe
Fix linter: remove placeholder, fix DVI reg declarations
2026-06-24 21:41:05 +08:00
5972facc0a
Pipeline matmul multiplier: 2-stage to fix WNS
...
Split compute into stage1 (compute → partial) and
stage2 (partial → c_data). Halves CARRY4 chain depth
from 16 to ~8 levels. Compute cycles: 16 → 32.
2026-06-24 21:40:34 +08:00
5ee2833a2b
Remove FFT module, tie off slave 6, fix linter issues
2026-06-24 20:54:33 +08:00
db2ad12dbb
Add verilator pragma to suppress BLKLOOPINIT in DelayBuffer.v
2026-06-24 20:41:52 +08:00
ff6e572996
matmul_test: rewrite for ExtRAM flow, add IP error debug
...
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
via matmul IP, write results back. Matches testbench
expectation of 10 groups.
- Add in matmul_axi_slave to trace error writes
2026-06-24 01:49:02 +08:00
fe8eff0aa0
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
fbc993b846
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
