fallensigh/ciciec2026
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16 Commits 5 Branches 1 Tag
3269e83d687fe35503aff61c4ca1f9c22982a8bd
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4 Commits

Author SHA1 Message Date
FallenSigh
3269e83d68 Debug: check ExtRAM write-back at start/mid/end of range 2026-06-24 22:36:29 +08:00
FallenSigh
4a67ca5c83 Add debug output for group 0 write-back and group 1 compute 2026-06-24 22:09:06 +08:00
FallenSigh
aaefb04737 Sync asm/ (user-sample.c + Makefile) from test branch 
MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.
 2026-06-24 17:01:45 +08:00
FallenSigh
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00