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2e4817fea6
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set sysclk to 60Mhz
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2026-07-14 22:50:44 +08:00 |
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99e6c884d7
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chore: untrack auto-generated PLL files, add .gitignore
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2026-06-30 02:10:29 +08:00 |
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542495cb52
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fix: replace UNUSEDPARAM/UNUSEDSIGNAL with UNUSED for verilator lint
Verilator does not recognize UNUSEDPARAM or UNUSEDSIGNAL.
Correct suppression code is UNUSED.
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2026-06-30 02:10:07 +08:00 |
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fe8eff0aa0
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Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
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2026-06-23 01:33:56 +08:00 |
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fbc993b846
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Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
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2026-06-23 01:22:45 +08:00 |
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