3 Commits

Author	SHA1	Message	Date
FallenSigh	c37f493bcb	Compute matmul CRC before result store	2026-07-04 19:45:22 +08:00
FallenSigh	b7553418fa	Add direct CDMA matmul path	2026-07-04 19:15:34 +08:00
FallenSigh	e35fa5884d	Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache ... The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000 go to the write-back data cache and never reach the SRAM model before the testbench checks ExtRAM. Use the 0xA0000000 uncached segment (same pattern as fft_dma/main.c).	2026-06-24 02:04:40 +08:00