From f735f789d6c2b5d0ff651c6f5917df5f47029e78 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Sat, 4 Jul 2026 21:20:32 +0800 Subject: [PATCH] remove dsp usage --- rtl/ip/cdma/cdma_matmul_bridge.sv | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/rtl/ip/cdma/cdma_matmul_bridge.sv b/rtl/ip/cdma/cdma_matmul_bridge.sv index bca9dd5..65d9399 100644 --- a/rtl/ip/cdma/cdma_matmul_bridge.sv +++ b/rtl/ip/cdma/cdma_matmul_bridge.sv @@ -98,6 +98,9 @@ module cdma_matmul_bridge #( logic [1:0] bank_store_pending; logic [1:0] bank_store_active; logic [31:0] bank_group_idx [2]; + logic [31:0] load_next_src_addr; + logic [31:0] load_next_dst_addr; + logic [31:0] bank_dst_addr [2]; logic rd_busy; logic wr_busy; @@ -250,6 +253,10 @@ module cdma_matmul_bridge #( bank_store_active <= 2'b00; bank_group_idx[0] <= 32'd0; bank_group_idx[1] <= 32'd0; + load_next_src_addr <= 32'd0; + load_next_dst_addr <= 32'd0; + bank_dst_addr[0] <= 32'd0; + bank_dst_addr[1] <= 32'd0; rd_busy <= 1'b0; wr_busy <= 1'b0; rd_active_bank <= 1'b0; @@ -302,6 +309,10 @@ module cdma_matmul_bridge #( bank_store_active <= 2'b00; bank_group_idx[0] <= 32'd0; bank_group_idx[1] <= 32'd0; + load_next_src_addr <= seq_src_base; + load_next_dst_addr <= seq_dst_base; + bank_dst_addr[0] <= 32'd0; + bank_dst_addr[1] <= 32'd0; rd_busy <= 1'b0; wr_busy <= 1'b0; compute_q <= 2'b00; @@ -344,7 +355,7 @@ module cdma_matmul_bridge #( end if (!rd_busy && !cdma_rd_req_valid && (load_next_idx < seq_groups) && load_target_free) begin - cdma_rd_req_src <= seq_src_base + (load_next_idx * seq_src_stride); + cdma_rd_req_src <= load_next_src_addr; cdma_rd_req_bytes <= MAT_AB_BYTES; cdma_rd_req_ep_id <= 4'd0; cdma_rd_req_ep_bank <= {3'b000, load_target_bank}; @@ -354,11 +365,14 @@ module cdma_matmul_bridge #( rd_active_bank <= load_target_bank; bank_load_active[load_target_bank] <= 1'b1; bank_group_idx[load_target_bank] <= load_next_idx; + bank_dst_addr[load_target_bank] <= load_next_dst_addr; + load_next_src_addr <= load_next_src_addr + seq_src_stride; + load_next_dst_addr <= load_next_dst_addr + seq_dst_stride; load_next_idx <= load_next_idx + 32'd1; end if (!seq_skip_writeback && !wr_busy && !cdma_wr_req_valid && store_ready_any) begin - cdma_wr_req_dst <= seq_dst_base + (bank_group_idx[store_sel_bank] * seq_dst_stride); + cdma_wr_req_dst <= bank_dst_addr[store_sel_bank]; cdma_wr_req_bytes <= MAT_C_BYTES; cdma_wr_req_ep_id <= 4'd0; cdma_wr_req_ep_bank <= {3'b000, store_sel_bank};