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Add timing instrumentation for profiling (prologue/loop/epilogue/crc32)

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FallenSigh
2026-06-25 20:10:31 +08:00
parent 956cd67773
commit d9483a9d39
1 changed files with 16 additions and 1 deletions
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17
sdk/software/examples/asm/user-sample.c
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@@ -160,7 +160,7 @@ int main(void)
if (MATMUL_GROUP_NUM <= 0) return 0; if (MATMUL_GROUP_NUM <= 0) return 0;
volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE_UNCACHED; volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE_UNCACHED;
uint32_t crc; uint32_t crc, t_prologue, t_mainloop, t_epilogue, t_crc32;
int g; int g;
// Ping-Pong Register Address Arrays (Physical for DMA) // Ping-Pong Register Address Arrays (Physical for DMA)
@@ -177,14 +177,17 @@ int main(void)
REG_WR(MATMUL_STATUS, STATUS_DONE | STATUS_ERROR); REG_WR(MATMUL_STATUS, STATUS_DONE | STATUS_ERROR);
/* ── Prologue: 第0组数据初始化 ────────────────────────── */ /* ── Prologue: 第0组数据初始化 ────────────────────────── */
t_prologue = get_ns();
// DMA Ch0: 从 ExtRAM 将 Group 0 的 A、B (128 bytes) 搬入 IP 的 Bank 0 // DMA Ch0: 从 ExtRAM 将 Group 0 的 A、B (128 bytes) 搬入 IP 的 Bank 0
dma_start_transfer(0, EXTRAM_PHYS_AB(0), phys_bank_AB[0], 128, 10); dma_start_transfer(0, EXTRAM_PHYS_AB(0), phys_bank_AB[0], 128, 10);
wait_dma_done_intr(0); wait_dma_done_intr(0);
// 启动 IP Bank 0 计算 // 启动 IP Bank 0 计算
REG_WR(MATMUL_CTRL, ctrl_start[0]); REG_WR(MATMUL_CTRL, ctrl_start[0]);
t_prologue = get_ns() - t_prologue;
/* ── Main Loop: 硬件完全流水线 (Overlapped Execution) ──── */ /* ── Main Loop: 硬件完全流水线 (Overlapped Execution) ──── */
t_mainloop = get_ns();
// 在 g 循环中: // 在 g 循环中:
// IP 正在计算 prev_bank (g-1) // IP 正在计算 prev_bank (g-1)
// DMA_CH0 正在加载 cur_bank (g) // DMA_CH0 正在加载 cur_bank (g)
@@ -213,21 +216,33 @@ int main(void)
// 6. 立即启动当前组在 IP 中的计算 // 6. 立即启动当前组在 IP 中的计算
REG_WR(MATMUL_CTRL, ctrl_start[cur_bank]); REG_WR(MATMUL_CTRL, ctrl_start[cur_bank]);
} }
t_mainloop = get_ns() - t_mainloop;
/* ── Epilogue: 收尾最后一组 ───────────────────────────── */ /* ── Epilogue: 收尾最后一组 ───────────────────────────── */
t_epilogue = get_ns();
wait_matmul_done_intr(); // 等待最后一次计算完成 wait_matmul_done_intr(); // 等待最后一次计算完成
wait_dma_done_intr(1); // 确保之前的 DMA CH1 空闲 wait_dma_done_intr(1); // 确保之前的 DMA CH1 空闲
// DMA CH1 将最后一组结果写回 // DMA CH1 将最后一组结果写回
dma_start_transfer(1, phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2], EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1), 192, 20); dma_start_transfer(1, phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2], EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1), 192, 20);
wait_dma_done_intr(1); wait_dma_done_intr(1);
t_epilogue = get_ns() - t_epilogue;
/* ── CRC32 over result region ─────────────────────────────── */ /* ── CRC32 over result region ─────────────────────────────── */
t_crc32 = get_ns();
crc = compute_crc32(extram); crc = compute_crc32(extram);
t_crc32 = get_ns() - t_crc32;
/* ── Final markers ────────────────────────────────────────── */ /* ── Final markers ────────────────────────────────────────── */
printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc); printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc);
printf("MATMUL_DONE\n"); printf("MATMUL_DONE\n");
printf("TIME_PROLOGUE=%lu\n", (unsigned long)t_prologue);
printf("TIME_LOOP=%lu\n", (unsigned long)t_mainloop);
printf("TIME_LOOP_PER=%lu\n", (unsigned long)(t_mainloop / MATMUL_GROUP_NUM));
printf("TIME_EPILOGUE=%lu\n", (unsigned long)t_epilogue);
printf("TIME_CRC32=%lu\n", (unsigned long)t_crc32);
printf("TIME_TOTAL=%lu\n", (unsigned long)(t_prologue + t_mainloop + t_epilogue + t_crc32));
return 0; return 0;
} }