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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:52 2026
| Host : fedora running 64-bit unknown
| Command : report_cdc -file ./vivado_reports/impl_cdc.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------
CDC Report
Severity Source Clock Destination Clock CDC Type Exceptions Endpoints Safe Unsafe Unknown No ASYNC_REG
-------- ------------ ----------------- ------------ ------------------- --------- ---- ------ ------- ------------
Critical sys_clk cpu_clk User Ignored Asynch Clock Groups 57 55 2 0 1
Warning cpu_clk sys_clk User Ignored Asynch Clock Groups 153 153 0 0 0

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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:51 2026
| Host : fedora running 64-bit unknown
| Command : report_clock_networks -file ./vivado_reports/impl_clock_networks.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
--------------------------------------------------------------------------------------
Clock Networks Report
Constrained Clocks
-------------------
Clock clk (50MHz)(endpoints: 17477 clock, 2 nonclock)
Port clk
Unconstrained Clocks
-------------------
Clock Q (endpoints: 23490 clock, 1 nonclock)
FDCE/Q (u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg)

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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:50 2026
| Host : fedora running 64-bit unknown
| Command : report_clock_utilization -file ./vivado_reports/impl_clock_utilization.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Synthesized
--------------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Device Cell Placement Summary for Global Clock g1
8. Device Cell Placement Summary for Global Clock g2
9. Device Cell Placement Summary for Global Clock g3
10. Clock Region Cell Placement per Global Clock: Region X0Y3
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 4 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 120 | 0 | 0 | 0 |
| BUFIO | 0 | 40 | 0 | 0 | 0 |
| BUFMR | 0 | 20 | 0 | 0 | 0 |
| BUFR | 0 | 40 | 0 | 0 | 0 |
| MMCM | 0 | 10 | 0 | 0 | 0 |
| PLL | 1 | 10 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
| g0 | src0 | BUFG/O | None | | n/a | 0 | 23490 | 0 | | | r_wb_reg[7]_i_3/O | u_mlkem_axi_slave/mlkem_clk |
| g1 | src1 | BUFG/O | None | | n/a | 1 | 10604 | 1 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/clkout2_buf/O | pll_clk.u_clk_pll/inst/sys_clk |
| g2 | src1 | BUFG/O | None | | n/a | 0 | 5859 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/clkout1_buf/O | pll_clk.u_clk_pll/inst/cpu_clk |
| g3 | src1 | BUFG/O | None | | n/a | 0 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkf_buf/O | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
| src0 | g0 | FDCE/Q | None | | n/a | 1 | 1 | | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg_0 |
| src1 | g3 | PLLE2_ADV/CLKFBOUT | None | | n/a | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |
| src1 | g2 | PLLE2_ADV/CLKOUT0 | None | | n/a | 1 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll |
| src1 | g1 | PLLE2_ADV/CLKOUT1 | None | | n/a | 1 | 0 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 | pll_clk.u_clk_pll/inst/sys_clk_clk_pll |
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y3 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 1 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
| g0 | BUFG/O | n/a | | | | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
7. Device Cell Placement Summary for Global Clock g1
----------------------------------------------------
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| g1 | BUFG/O | n/a | sys_clk | 20.000 | {0.000 10.000} | 0 | 1 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 1 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
8. Device Cell Placement Summary for Global Clock g2
----------------------------------------------------
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| g2 | BUFG/O | n/a | cpu_clk | 30.323 | {0.000 15.161} | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
9. Device Cell Placement Summary for Global Clock g3
----------------------------------------------------
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
| g3 | BUFG/O | n/a | clkfbout_clk_pll | 20.000 | {0.000 10.000} | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
10. Clock Region Cell Placement per Global Clock: Region X0Y3
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
| g1 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of IO Primitives which is load of clock spine
set_property LOC IOB_X0Y173 [get_cells video_clk_OBUF_inst]
# Location of clock ports
set_property LOC IOB_X0Y176 [get_ports clk]

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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:38:45 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -timing -logic_level_distribution -file ./vivado_reports/impl_design_analysis.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Synthesized
--------------------------------------------------------------------------------------------------------------------------
Report Design Analysis
Table of Contents
-----------------
1. Setup Path Characteristics 1-1
2. Logic Level Distribution
1. Setup Path Characteristics 1-1
---------------------------------
+---------------------------+-----------------------------------------------------------------------------------------------------------+
| Characteristics | Path #1 |
+---------------------------+-----------------------------------------------------------------------------------------------------------+
| Requirement | 20.000 |
| Path Delay | 17.702 |
| Logic Delay | 4.444(26%) |
| Net Delay | 13.258(74%) |
| Clock Skew | -0.145 |
| Slack | 2.111 |
| Clock Relationship | Safely Timed |
| Logic Levels | 18 |
| Routes | 0 |
| Logical Path | FDRE LUT2 CARRY4 CARRY4 LUT2 CARRY4 LUT6 LUT6 LUT6 LUT6 LUT6 LUT5 LUT6 LUT5 LUT5 LUT5 LUT5 LUT6 LUT6 FDSE |
| Start Point Clock | sys_clk |
| End Point Clock | sys_clk |
| DSP Block | None |
| BRAM | None |
| IO Crossings | 0 |
| Config Crossings | 0 |
| SLR Crossings | 0 |
| PBlocks | 0 |
| High Fanout | 16 |
| Dont Touch | 0 |
| Mark Debug | 0 |
| Start Point Pin Primitive | FDRE/C |
| End Point Pin Primitive | FDSE/D |
| Start Point Pin | p_reg[1]/C |
| End Point Pin | crc_reg_reg[18]/D |
+---------------------------+-----------------------------------------------------------------------------------------------------------+
* Bounding box calculated as % of dimensions for the target device (436, 500)
2. Logic Level Distribution
---------------------------
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
| End Point Clock | Requirement | 10 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 29 | 30 | 31 | 32 |
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
| cpu_clk | 30.323ns | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 65 | 40 | 34 | 62 |
| sys_clk | 20.000ns | 2 | 120 | 72 | 122 | 348 | 89 | 7 | 37 | 1 | 1 | 0 | 0 | 0 | 0 |
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
* Columns represent the logic levels per end point clock
** Distribution is for top worst 1000 paths

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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:54 2026
| Host : fedora running 64-bit unknown
| Command : report_drc -file ./vivado_reports/impl_drc.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Speed File : -1
| Design State : Synthesized
------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 42
+-----------+----------+----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+----------------------------+------------+
| CHECK-3 | Warning | Report rule limit reached | 2 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
| REQP-1840 | Warning | RAMB18 async control check | 20 |
+-----------+----------+----------------------------+------------+
2. REPORT DETAILS
-----------------
CHECK-3#1 Warning
Report rule limit reached
REQP-1839 rule limit reached: 20 violations have been found.
Related violations: <none>
CHECK-3#2 Warning
Report rule limit reached
REQP-1840 rule limit reached: 20 violations have been found.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#9 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#10 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#11 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#12 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#13 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#14 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#15 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#16 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#17 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#18 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#19 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#20 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#1 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#2 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#3 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#4 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#5 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#6 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#7 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#8 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#9 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#10 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#11 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#12 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#13 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#14 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#15 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#16 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#17 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#18 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#19 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#20 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

121
fpga/vivado_reports/impl_high_fanout_nets.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:38:35 2026
| Host : fedora running 64-bit unknown
| Command : report_high_fanout_nets -max_nets 100 -file ./vivado_reports/impl_high_fanout_nets.rpt
| Design : soc_top
| Device : xc7a200t
--------------------------------------------------------------------------------------------------------
High Fan-out Nets Information
1. Summary
----------
+---------------------------------------------------------------------------------------+--------+-------------+
| Net Name | Fanout | Driver Type |
+---------------------------------------------------------------------------------------+--------+-------------+
| pll_clk.u_rst_sys/p_0_in | 28767 | LUT1 |
| pll_clk.u_clk_pll/inst/sys_clk | 10994 | BUFG |
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2097 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1614 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1608 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/sha3_ack_reg | 1604 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_snt | 1602 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_snt/state_next[1] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_snt/state_next[2] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_2 | 1122 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[1]_rep__0_13 | 1088 | LUT5 |
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[2] | 1080 | FDRE |
| u_matmul_axi_slave/w_addr[2] | 879 | FDRE |
| u_matmul_axi_slave/w_addr[3] | 874 | FDRE |
| u_cpu/reset | 799 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg_n_0_[0] | 788 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg_n_0_[1] | 787 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[0] | 774 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[1] | 774 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[3] | 773 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 772 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 771 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/comp_k_reg[0]_rep_n_0 | 771 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/comp_k_reg[1]_rep_n_0 | 771 | FDCE |
| u_cpu/u_mul/E[0] | 716 | LUT1 |
| u_matmul_axi_slave/current_r_offset[2] | 525 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/r_r | 512 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
| u_matmul_axi_slave/w_addr[4] | 438 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[2] | 390 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[4] | 388 | FDCE |
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 329 | LUT3 |
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 321 | LUT3 |
| u_matmul_axi_slave/w_addr[5] | 303 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rho_r1 | 294 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/pre_addr_l_reg[7]_0[0] | 288 | CARRY4 |
| u_matmul_axi_slave/sel0[0] | 262 | FDRE |
| u_matmul_axi_slave/sel0[1] | 261 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 260 | LUT5 |
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 260 | LUT2 |
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[2] | 260 | FDRE |
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[3] | 259 | FDRE |
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 258 | LUT3 |
| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 257 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_1[0] | 256 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT2 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 239 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 239 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 237 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 237 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 237 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 237 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 237 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 235 | RAMB36E1 |
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
| u_cpu/mem_stage/E[0] | 232 | LUT1 |
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
+---------------------------------------------------------------------------------------+--------+-------------+

718
fpga/vivado_reports/impl_io.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:36:08 2026
| Host : fedora running 64-bit unknown
| Command : report_io -file ./vivado_reports/impl_io.rpt
| Design : soc_top
| Device : xc7a200t
| Speed File : -1
| Package : fbg676
| Package Version : FINAL 2012-06-20
| Package Pin Delay Version : FINAL VERS. 2.0 2012-06-20
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 202 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| A2 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| A3 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| A4 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| A5 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A7 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A9 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
| A10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A11 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
| A14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A15 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A17 | dpy1[0] | High Range | IO_L9P_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A18 | leds[11] | High Range | IO_L9N_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A19 | dpy0[3] | High Range | IO_L10N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A20 | leds[14] | High Range | IO_L15N_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| A22 | leds[13] | High Range | IO_L17N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A23 | leds[9] | High Range | IO_L21P_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A24 | leds[2] | High Range | IO_L21N_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A25 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA1 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AA2 | | High Range | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA3 | | High Range | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA4 | | High Range | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA5 | | High Range | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA7 | | High Range | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA8 | | High Range | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA10 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AA11 | | | MGTREFCLK1P_213 | Gigabit | | | | | | | | | | | | | | | |
| AA12 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AA13 | | | MGTREFCLK0P_213 | Gigabit | | | | | | | | | | | | | | | |
| AA14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA15 | ext_ram_data[23] | High Range | IO_L23N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA17 | ext_ram_addr[8] | High Range | IO_L19P_T3_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA18 | ext_ram_addr[7] | High Range | IO_L17N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA19 | ext_ram_data[30] | High Range | IO_L13P_T2_MRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA20 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AA22 | base_ram_addr[14] | High Range | IO_L8P_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA23 | base_ram_addr[11] | High Range | IO_L8N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA24 | base_ram_data[8] | High Range | IO_L7P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA25 | ext_ram_addr[10] | High Range | IO_L5N_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB1 | | High Range | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB2 | | High Range | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB4 | | High Range | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB5 | | High Range | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB6 | | High Range | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| AB8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB11 | | | MGTREFCLK1N_213 | Gigabit | | | | | | | | | | | | | | | |
| AB12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB13 | | | MGTREFCLK0N_213 | Gigabit | | | | | | | | | | | | | | | |
| AB14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB15 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | |
| AB16 | ext_ram_data[16] | High Range | IO_L22P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB17 | ext_ram_data[18] | High Range | IO_L19N_T3_VREF_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB18 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AB19 | ext_ram_oe_n | High Range | IO_L13N_T2_MRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB20 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
| AB21 | ext_ram_data[27] | High Range | IO_L11P_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB22 | ext_ram_be_n[3] | High Range | IO_0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB24 | base_ram_addr[10] | High Range | IO_L9P_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB25 | ext_ram_addr[12] | High Range | IO_L7N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB26 | ext_ram_addr[11] | High Range | IO_L3P_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC1 | | High Range | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC2 | | High Range | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC3 | | High Range | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC4 | | High Range | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC5 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AC6 | | High Range | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC8 | | | MGTPTXP2_213 | Gigabit | | | | | | | | | | | | | | | |
| AC9 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC10 | | | MGTPTXP0_213 | Gigabit | | | | | | | | | | | | | | | |
| AC11 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC12 | | | MGTPRXP0_213 | Gigabit | | | | | | | | | | | | | | | |
| AC13 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC14 | | | MGTPRXP2_213 | Gigabit | | | | | | | | | | | | | | | |
| AC15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC16 | ext_ram_data[21] | High Range | IO_L22N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC17 | ext_ram_data[25] | High Range | IO_L20P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC18 | ext_ram_data[19] | High Range | IO_L15P_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC19 | ext_ram_data[17] | High Range | IO_L14P_T2_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC21 | ext_ram_data[29] | High Range | IO_L11N_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC22 | ext_ram_addr[5] | High Range | IO_L2P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC23 | ext_ram_data[31] | High Range | IO_L2N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC24 | ext_ram_addr[14] | High Range | IO_L9N_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| AC26 | ext_ram_addr[13] | High Range | IO_L3N_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD1 | | High Range | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD2 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AD3 | | High Range | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD4 | | High Range | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD5 | | High Range | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD7 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AD8 | | | MGTPTXN2_213 | Gigabit | | | | | | | | | | | | | | | |
| AD9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD10 | | | MGTPTXN0_213 | Gigabit | | | | | | | | | | | | | | | |
| AD11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD12 | | | MGTPRXN0_213 | Gigabit | | | | | | | | | | | | | | | |
| AD13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD14 | | | MGTPRXN2_213 | Gigabit | | | | | | | | | | | | | | | |
| AD15 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AD16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD17 | ext_ram_data[24] | High Range | IO_L20N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD18 | ext_ram_data[20] | High Range | IO_L15N_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD19 | ext_ram_we_n | High Range | IO_L14N_T2_SRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD20 | ext_ram_data[26] | High Range | IO_L10P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD21 | ext_ram_data[28] | High Range | IO_L7P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AD23 | ext_ram_ce_n | High Range | IO_L6P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD24 | ext_ram_be_n[2] | High Range | IO_L6N_T0_VREF_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD25 | ext_ram_addr[3] | High Range | IO_L4P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD26 | ext_ram_addr[4] | High Range | IO_L4N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE1 | | High Range | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE2 | | High Range | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE3 | | High Range | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE5 | | High Range | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE7 | | | MGTPTXP3_213 | Gigabit | | | | | | | | | | | | | | | |
| AE8 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE9 | | | MGTPTXP1_213 | Gigabit | | | | | | | | | | | | | | | |
| AE10 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE11 | | | MGTPRXP3_213 | Gigabit | | | | | | | | | | | | | | | |
| AE12 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE13 | | | MGTPRXP1_213 | Gigabit | | | | | | | | | | | | | | | |
| AE14 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE16 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| AE17 | ext_ram_addr[16] | High Range | IO_L18P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE18 | ext_ram_addr[18] | High Range | IO_L16P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE19 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AE20 | ext_ram_data[6] | High Range | IO_L10N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE21 | ext_ram_data[5] | High Range | IO_L7N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE22 | ext_ram_data[3] | High Range | IO_L9P_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE23 | ext_ram_data[1] | High Range | IO_L5P_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE25 | ext_ram_addr[1] | High Range | IO_L1P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE26 | ext_ram_addr[2] | High Range | IO_L1N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF2 | | High Range | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF3 | | High Range | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF4 | | High Range | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF5 | | High Range | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF7 | | | MGTPTXN3_213 | Gigabit | | | | | | | | | | | | | | | |
| AF8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF9 | | | MGTPTXN1_213 | Gigabit | | | | | | | | | | | | | | | |
| AF10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF11 | | | MGTPRXN3_213 | Gigabit | | | | | | | | | | | | | | | |
| AF12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF13 | | | MGTPRXN1_213 | Gigabit | | | | | | | | | | | | | | | |
| AF14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF15 | | | MGTRREF_213 | Gigabit | | | | | | | | | | | | | | | |
| AF16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF17 | ext_ram_addr[15] | High Range | IO_L18N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF18 | ext_ram_addr[17] | High Range | IO_L16N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF19 | ext_ram_addr[19] | High Range | IO_L8P_T1_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF20 | ext_ram_data[7] | High Range | IO_L8N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF22 | ext_ram_data[4] | High Range | IO_L9N_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF23 | ext_ram_data[2] | High Range | IO_L5N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF24 | ext_ram_data[0] | High Range | IO_L3P_T0_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF25 | ext_ram_addr[0] | High Range | IO_L3N_T0_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| B1 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| B2 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B4 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| B5 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| B6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B7 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
| B8 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B9 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
| B10 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B11 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
| B12 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B13 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
| B14 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B17 | dpy0[6] | High Range | IO_L7N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| B19 | dpy0[0] | High Range | IO_L10P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B20 | leds[15] | High Range | IO_L15P_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B21 | dpy0[2] | High Range | IO_L16N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B22 | leds[7] | High Range | IO_L17P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B24 | leds[0] | High Range | IO_L23N_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B25 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B26 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C1 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| C2 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| C3 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| C4 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| C5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C7 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| C8 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C10 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
| C11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C12 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
| C13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C14 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
| C15 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C17 | dpy0[7] | High Range | IO_L7P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C18 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C19 | dpy0[5] | High Range | IO_L13N_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C21 | leds[5] | High Range | IO_L16P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C22 | leds[4] | High Range | IO_L19P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C23 | leds[8] | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C24 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C25 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| C26 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| D2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| D3 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| D4 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| D5 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| D6 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D8 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
| D9 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D10 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
| D11 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D12 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
| D13 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D14 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
| D15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D16 | dpy1[1] | High Range | IO_L8N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D18 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| D19 | dpy0[1] | High Range | IO_L13P_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D20 | leds[12] | High Range | IO_L14N_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D21 | leds[10] | High Range | IO_L18N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| D23 | leds[3] | High Range | IO_L24P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D24 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D25 | video_blue[1] | High Range | IO_L20N_T3_A19_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D26 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| E2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| E3 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E5 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| E6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E11 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
| E12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E13 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E16 | dpy1[4] | High Range | IO_L8P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E17 | dpy1[2] | High Range | IO_L11P_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E18 | dpy0[4] | High Range | IO_L11N_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| E20 | leds[6] | High Range | IO_L14P_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E21 | leds[1] | High Range | IO_L18P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E22 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
| E23 | video_green[1] | High Range | IO_L17N_T2_A25_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E25 | video_blue[0] | High Range | IO_L20P_T3_A20_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E26 | video_red[2] | High Range | IO_L21P_T3_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| F3 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| F4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| F5 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| F6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| F7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| F8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F10 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| F11 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
| F12 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| F13 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
| F14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F15 | dpy1[6] | High Range | IO_L4N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F16 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| F17 | dpy1[3] | High Range | IO_L2N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F18 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F19 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F20 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| F23 | video_green[2] | High Range | IO_L17P_T2_A26_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F24 | video_red[1] | High Range | IO_L19N_T3_A21_VREF_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F25 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| F26 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| G1 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| G2 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| G3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| G4 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| G5 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| G6 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G7 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G8 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G9 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G14 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| G15 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| G16 | dpy1[5] | High Range | IO_L6N_T0_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G17 | dpy1[7] | High Range | IO_L2P_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G19 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| G20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| G21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| G22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| G23 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| G24 | video_de | High Range | IO_L19P_T3_A22_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G25 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G26 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| H1 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| H2 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| H3 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
| H4 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H7 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H8 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H9 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| H10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| H11 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| H12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| H13 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| H14 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H15 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H16 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H17 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H18 | UART_TX | High Range | IO_L10N_T1_AD11N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H19 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| H21 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| H22 | video_clk | High Range | IO_L13N_T2_MRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H23 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| H24 | video_vsync | High Range | IO_L16N_T2_A27_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H26 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| J1 | dip_sw[14] | High Range | IO_L7N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J3 | dip_sw[1] | High Range | IO_L1N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| J4 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
| J5 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
| J6 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| J8 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
| J9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| J10 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J14 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J15 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| J16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| J18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J19 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J20 | UART_RX | High Range | IO_L9N_T1_DQS_AD3N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| J21 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J23 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| J24 | video_hsync | High Range | IO_L16P_T2_A28_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| J25 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| J26 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| K1 | dip_sw[17] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K2 | dip_sw[16] | High Range | IO_L8N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K3 | dip_sw[13] | High Range | IO_L1P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| K5 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K6 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
| K7 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
| K8 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| K15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K16 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| K18 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K20 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K21 | clk | High Range | IO_L12P_T1_MRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
| K22 | video_green[0] | High Range | IO_L18P_T2_A24_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K23 | video_red[0] | High Range | IO_L18N_T2_A23_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K24 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| K25 | base_ram_be_n[3] | High Range | IO_L7P_T1_D09_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K26 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| L2 | dip_sw[15] | High Range | IO_L11N_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L3 | dip_sw[6] | High Range | IO_L8P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L4 | dip_sw[19] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L5 | dip_sw[5] | High Range | IO_L4P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L7 | dip_sw[11] | High Range | IO_L2N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L8 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
| L9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L14 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| L15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L17 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| L18 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| L19 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| L20 | base_ram_be_n[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| L22 | base_ram_be_n[1] | High Range | IO_L11P_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L23 | base_ram_be_n[2] | High Range | IO_L11N_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L24 | base_ram_data[0] | High Range | IO_L9P_T1_DQS_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L25 | base_ram_data[1] | High Range | IO_L9N_T1_DQS_D13_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M1 | touch_btn[1] | High Range | IO_L9N_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M2 | dip_sw[2] | High Range | IO_L11P_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M4 | dip_sw[20] | High Range | IO_L3P_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M5 | dip_sw[12] | High Range | IO_L6N_T0_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M6 | dip_sw[8] | High Range | IO_L6P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M7 | dip_sw[10] | High Range | IO_L2P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M14 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| M15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| M16 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| M19 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| M20 | base_ram_data[21] | High Range | IO_L8P_T1_D11_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M21 | base_ram_data[17] | High Range | IO_L12P_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M22 | base_ram_data[31] | High Range | IO_L12N_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M24 | base_ram_data[30] | High Range | IO_L10P_T1_D14_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M25 | base_ram_data[3] | High Range | IO_L10N_T1_D15_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M26 | base_ram_data[2] | High Range | IO_L20N_T3_A07_D23_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N1 | dip_sw[23] | High Range | IO_L9P_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N2 | dip_sw[21] | High Range | IO_L12N_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N3 | dip_sw[18] | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N4 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| N5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| N6 | dip_sw[7] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N7 | dip_sw[9] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N8 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| N14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| N15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| N16 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| N17 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | base_ram_data[20] | High Range | IO_L16N_T2_A15_D31_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N21 | base_ram_data[23] | High Range | IO_L13P_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N22 | base_ram_data[28] | High Range | IO_L13N_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N23 | base_ram_data[29] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N24 | base_ram_data[22] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| N26 | base_ram_data[4] | High Range | IO_L20P_T3_A08_D24_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P1 | dip_sw[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| P3 | touch_btn[2] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P4 | dip_sw[4] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P5 | dip_sw[24] | High Range | IO_L19N_T3_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P6 | dip_sw[22] | High Range | IO_L19P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| P15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P18 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P19 | base_ram_data[19] | High Range | IO_L16P_T2_CSI_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P20 | base_ram_data[27] | High Range | IO_L14P_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P21 | base_ram_data[16] | High Range | IO_L14N_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| P23 | base_ram_data[18] | High Range | IO_L17P_T2_A14_D30_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P24 | base_ram_data[5] | High Range | IO_L17N_T2_A13_D29_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P25 | base_ram_data[7] | High Range | IO_L19N_T3_A09_D25_VREF_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P26 | base_ram_data[6] | High Range | IO_L22N_T3_A04_D20_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R1 | dip_sw[27] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R2 | dip_sw[31] | High Range | IO_L17N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R3 | dip_sw[25] | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R5 | dip_sw[28] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R6 | dip_sw[30] | High Range | IO_L23N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| R14 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| R15 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| R16 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| R17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| R18 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| R19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| R20 | base_ram_addr[5] | High Range | IO_L18P_T2_A12_D28_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R21 | base_ram_data[26] | High Range | IO_L18N_T2_A11_D27_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R22 | base_ram_data[25] | High Range | IO_L23N_T3_A02_D18_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R23 | base_ram_addr[6] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R25 | ext_ram_be_n[1] | High Range | IO_L19P_T3_A10_D26_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R26 | ext_ram_be_n[0] | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T2 | touch_btn[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T3 | dip_sw[0] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T4 | dip_sw[26] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T5 | dip_sw[29] | High Range | IO_L20P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| T7 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T14 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T15 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| T17 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| T18 | base_ram_addr[2] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T19 | base_ram_addr[0] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T20 | base_ram_oe_n | High Range | IO_L15P_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T22 | base_ram_data[24] | High Range | IO_L23P_T3_A03_D19_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T23 | base_ram_addr[7] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T24 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| T25 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| U1 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | touch_btn[3] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| U3 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| U4 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
| U5 | reset | High Range | IO_L21N_T3_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| U6 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U7 | | High Range | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| U14 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U15 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U16 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U17 | base_ram_addr[4] | High Range | IO_25_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U19 | base_ram_ce_n | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U20 | base_ram_we_n | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U21 | base_ram_data[15] | High Range | IO_L13P_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U22 | base_ram_addr[8] | High Range | IO_L12P_T1_MRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U23 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| U24 | ext_ram_data[15] | High Range | IO_0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U25 | ext_ram_data[13] | High Range | IO_L1P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U26 | ext_ram_data[14] | High Range | IO_L1N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V1 | | High Range | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V2 | | High Range | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V3 | | High Range | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V4 | | High Range | IO_0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V6 | | High Range | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V7 | | High Range | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| V8 | | High Range | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V9 | | High Range | IO_25_33 | User IO | | 33 | | | | | | | | | | | | | |
| V10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| V11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| V12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V14 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V16 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| V17 | base_ram_addr[3] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V18 | base_ram_addr[1] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V19 | base_ram_addr[19] | High Range | IO_L18P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| V21 | base_ram_data[10] | High Range | IO_L13N_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V22 | base_ram_data[13] | High Range | IO_L12N_T1_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V23 | base_ram_data[14] | High Range | IO_L10P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V24 | ext_ram_data[11] | High Range | IO_L6P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V26 | ext_ram_data[12] | High Range | IO_L2P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W1 | | High Range | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W3 | | High Range | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W4 | | High Range | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W5 | | High Range | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W6 | | High Range | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W7 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| W8 | | High Range | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| W9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| W10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| W11 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| W14 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
| W15 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
| W16 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | |
| W17 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| W18 | base_ram_addr[18] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W19 | base_ram_addr[15] | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W20 | base_ram_addr[17] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W21 | base_ram_addr[16] | High Range | IO_L14P_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W23 | base_ram_data[12] | High Range | IO_L10N_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W24 | base_ram_data[11] | High Range | IO_L6N_T0_VREF_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W25 | ext_ram_data[9] | High Range | IO_L4P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W26 | ext_ram_data[10] | High Range | IO_L2N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y1 | | High Range | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y2 | | High Range | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y3 | | High Range | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y4 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| Y5 | | High Range | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y6 | | High Range | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y7 | | High Range | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y8 | | High Range | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y9 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| Y10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y14 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
| Y15 | ext_ram_data[22] | High Range | IO_L23P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y16 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
| Y17 | ext_ram_addr[6] | High Range | IO_L21N_T3_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y18 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y20 | base_ram_addr[13] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y21 | base_ram_addr[12] | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y22 | base_ram_addr[9] | High Range | IO_L11P_T1_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y23 | base_ram_data[9] | High Range | IO_L11N_T1_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| Y25 | ext_ram_addr[9] | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y26 | ext_ram_data[8] | High Range | IO_L4N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

5531
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:41 2026
| Host : fedora running 64-bit unknown
| Command : report_power -file ./vivado_reports/impl_power.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Design State : synthesized
| Grade : commercial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.727 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.586 |
| Device Static (W) | 0.141 |
| Effective TJA (C/W) | 1.9 |
| Max Ambient (C) | 83.6 |
| Junction Temperature (C) | 26.4 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.030 | 6 | --- | --- |
| Slice Logic | 0.180 | 137345 | --- | --- |
| LUT as Logic | 0.172 | 73234 | 134600 | 54.41 |
| CARRY4 | 0.005 | 3590 | 33650 | 10.67 |
| LUT as Distributed RAM | 0.001 | 652 | 46200 | 1.41 |
| Register | 0.001 | 38603 | 269200 | 14.34 |
| LUT as Shift Register | <0.001 | 1094 | 46200 | 2.37 |
| F7/F8 Muxes | <0.001 | 5666 | 134600 | 4.21 |
| BUFG | <0.001 | 1 | 32 | 3.13 |
| Others | 0.000 | 287 | --- | --- |
| Signals | 0.190 | 113832 | --- | --- |
| Block RAM | 0.020 | 25.5 | 365 | 6.99 |
| PLL | 0.137 | 1 | 10 | 10.00 |
| I/O | 0.029 | 202 | 400 | 50.50 |
| Static Power | 0.141 | | | |
| Total | 0.727 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 0.465 | 0.432 | 0.032 |
| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 |
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | Low | Design is synthesized | Accuracy of the tool is not optimal until design is fully placed and routed |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 1.9 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 3.4 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+------------------+-----------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------------+-----------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+------------------+-----------------------------------------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+----------------------------+-----------+
| Name | Power (W) |
+----------------------------+-----------+
| soc_top | 0.586 |
| pll_clk.u_clk_pll | 0.138 |
| inst | 0.138 |
| u_AxiCrossbar_2x8 | 0.001 |
| u_Axi_CDC | 0.003 |
| u_axi_uart_controller | 0.002 |
| uart0 | 0.001 |
| regs | 0.001 |
| u_cdma_matmul_bridge | 0.001 |
| u_confreg | 0.001 |
| u_cpu | 0.026 |
| addr_trans | 0.002 |
| tlb_entry | 0.002 |
| btb | 0.003 |
| dcache | 0.004 |
| icache | 0.005 |
| u_csr | 0.001 |
| u_mul | 0.006 |
| u_fft_mlkem_axi_slave | 0.285 |
| u_fft_controller | 0.032 |
| u_FFT | 0.029 |
| u_out0 | 0.001 |
| u_out1 | 0.001 |
| u_mlkem_axi_slave | 0.250 |
| u_mlkem | 0.227 |
| u_prng_axi_slave | 0.004 |
| u_matmul_axi_slave | 0.072 |
| mult_inst[0].u_mult | 0.002 |
| mult_inst[1].u_mult | 0.002 |
| mult_inst[2].u_mult | 0.002 |
| mult_inst[3].u_mult | 0.002 |
| u_snix_axil_cdma_mux_8ch | 0.010 |
| u_core_engine | 0.005 |
| axis_fifo_u0 | 0.004 |
+----------------------------+-----------+

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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 158000 :
# of nets with no placed pins.......... : 157584 :
# of nets not needing routing.......... : 202 :
# of internally routed nets........ : 202 :
# of routable nets..................... : 0 :
# of nets with routing errors.......... : 214 :
# of nets with some unplaced pins.. : 214 :
# of nets with some unrouted pins.. : 160 :
------------------------------------------- : ----------- :
Nets with Routing Errors: (only the first 10 nets are listed)
GLOBAL_LOGIC0
Unplaced Pins -- only the first 10 are listed, use -show_all to get the full list:
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR2
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR3
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR4
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR2
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR3
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR4
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR2
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR3
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR4
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR2
UART_RX_IOBUF_inst/O
Unplaced Pin: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/I3
UART_TX_IOBUF_inst/O
Unplaced Pins:
u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/I2
u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/I0
u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/I1
u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/I2
base_ram_data_IOBUF[0]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_251__0/I4
base_ram_data_IOBUF[10]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_182/I4
base_ram_data_IOBUF[11]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_177__0/I4
base_ram_data_IOBUF[12]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_169__0/I4
base_ram_data_IOBUF[13]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_159__0/I4
base_ram_data_IOBUF[14]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_152__0/I4
base_ram_data_IOBUF[15]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_355__0/I4

93512
fpga/vivado_reports/impl_timing_summary_hold.rpt Normal file
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93999
fpga/vivado_reports/impl_timing_summary_setup.rpt Normal file
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203
fpga/vivado_reports/impl_utilization.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:22 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -file ./vivado_reports/impl_utilization.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs* | 74980 | 0 | 134600 | 55.71 |
| LUT as Logic | 73234 | 0 | 134600 | 54.41 |
| LUT as Memory | 1746 | 0 | 46200 | 3.78 |
| LUT as Distributed RAM | 652 | 0 | | |
| LUT as Shift Register | 1094 | 0 | | |
| Slice Registers | 38603 | 0 | 269200 | 14.34 |
| Register as Flip Flop | 38603 | 0 | 269200 | 14.34 |
| Register as Latch | 0 | 0 | 269200 | 0.00 |
| F7 Muxes | 4263 | 0 | 67300 | 6.33 |
| F8 Muxes | 1403 | 0 | 33650 | 4.17 |
+----------------------------+-------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 101 | Yes | - | Set |
| 25523 | Yes | - | Reset |
| 134 | Yes | Set | - |
| 12845 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
| RAMB36E1 only | 10 | | | |
| RAMB18 | 31 | 0 | 730 | 4.25 |
| RAMB18E1 only | 31 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 202 | 202 | 400 | 50.50 |
| IOB Master Pads | 97 | | | |
| IOB Slave Pads | 102 | | | |
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
| PHASER_REF | 0 | 0 | 10 | 0.00 |
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
| IN_FIFO | 0 | 0 | 40 | 0.00 |
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
| IBUFDS | 0 | 0 | 384 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
| ILOGIC | 0 | 0 | 400 | 0.00 |
| OLOGIC | 0 | 0 | 400 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
| BUFIO | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
| BUFMRCE | 0 | 0 | 20 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 40 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| LUT6 | 36042 | LUT |
| FDCE | 25523 | Flop & Latch |
| LUT5 | 16007 | LUT |
| LUT3 | 13060 | LUT |
| FDRE | 12845 | Flop & Latch |
| LUT4 | 11977 | LUT |
| LUT2 | 9006 | LUT |
| MUXF7 | 4263 | MuxFx |
| CARRY4 | 3590 | CarryLogic |
| MUXF8 | 1403 | MuxFx |
| SRLC32E | 992 | Distributed Memory |
| RAMD32 | 892 | Distributed Memory |
| LUT1 | 816 | LUT |
| RAMS32 | 272 | Distributed Memory |
| FDSE | 134 | Flop & Latch |
| IBUF | 104 | IO |
| SRL16E | 102 | Distributed Memory |
| FDPE | 101 | Flop & Latch |
| OBUF | 98 | IO |
| OBUFT | 66 | IO |
| RAMD64E | 32 | Distributed Memory |
| RAMB18E1 | 31 | Block Memory |
| RAMB36E1 | 10 | Block Memory |
| BUFG | 4 | Clock |
| PLLE2_ADV | 1 | Clock |
+-----------+-------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
| clk_pll | 1 |
+----------+------+

255
fpga/vivado_reports/impl_utilization_hier.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:23 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports/impl_utilization_hier.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Synthesized
--------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Utilization by Hierarchy
1. Utilization by Hierarchy
---------------------------
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| soc_top | (top) | 74980 | 73234 | 652 | 1094 | 38603 | 10 | 31 | 0 |
| (soc_top) | (top) | 2116 | 2060 | 56 | 0 | 4 | 0 | 0 | 0 |
| pll_clk.u_clk_pll | clk_pll | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll_clk_pll_clk_wiz | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 519 | 519 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 61 | 61 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 25 | 25 | 0 | 0 | 14 | 0 | 0 | 0 |
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 505 | 377 | 128 | 0 | 309 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 262 | 226 | 36 | 0 | 73 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 256 | 220 | 36 | 0 | 61 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 112 | 76 | 36 | 0 | 75 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 105 | 69 | 36 | 0 | 61 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 16 | 16 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 9 | 9 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 69 | 41 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1355 | 1355 | 0 | 0 | 161 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 648 | 648 | 0 | 0 | 81 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 707 | 707 | 0 | 0 | 80 | 0 | 0 | 0 |
| u_axi_dvi | axi_dvi | 285 | 285 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 693 | 677 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 121 | 121 | 0 | 0 | 155 | 0 | 0 | 0 |
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
| receiver | uart_receiver | 231 | 223 | 8 | 0 | 124 | 0 | 0 | 0 |
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
| fifo_rx | uart_rfifo | 163 | 155 | 8 | 0 | 70 | 0 | 0 | 0 |
| (fifo_rx) | uart_rfifo | 144 | 144 | 0 | 0 | 62 | 0 | 0 | 0 |
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 86 | 78 | 8 | 0 | 56 | 0 | 0 | 0 |
| (transmitter) | uart_transmitter | 42 | 42 | 0 | 0 | 35 | 0 | 0 | 0 |
| fifo_tx | uart_tfifo | 44 | 36 | 8 | 0 | 21 | 0 | 0 | 0 |
| (fifo_tx) | uart_tfifo | 25 | 25 | 0 | 0 | 13 | 0 | 0 | 0 |
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_confreg | confreg | 391 | 391 | 0 | 0 | 460 | 0 | 0 | 0 |
| (u_confreg) | confreg | 231 | 231 | 0 | 0 | 383 | 0 | 0 | 0 |
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
| u_cpu | core_top | 8656 | 8380 | 276 | 0 | 5591 | 0 | 20 | 0 |
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2264 | 2100 | 164 | 0 | 1244 | 0 | 0 | 0 |
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2264 | 2100 | 164 | 0 | 1204 | 0 | 0 | 0 |
| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 |
| btb | btb | 1064 | 984 | 80 | 0 | 1611 | 0 | 0 | 0 |
| (btb) | btb | 1061 | 981 | 80 | 0 | 1611 | 0 | 0 | 0 |
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
| dcache | dcache | 569 | 537 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 92 | 60 | 32 | 0 | 138 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_46 | 46 | 46 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 650 | 650 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
| icache | icache | 239 | 239 | 0 | 0 | 55 | 0 | 10 | 0 |
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
| id_stage | id_stage | 1058 | 1058 | 0 | 0 | 108 | 0 | 0 | 0 |
| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 |
| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
| u_div | div | 143 | 143 | 0 | 0 | 107 | 0 | 0 | 0 |
| u_mul | mul | 943 | 943 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 685 | 685 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 48074 | 46986 | 0 | 1088 | 25915 | 10 | 10 | 0 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 6966 | 5878 | 0 | 1088 | 1087 | 8 | 4 | 0 |
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
| u_FFT | FFT | 6855 | 5767 | 0 | 1088 | 983 | 8 | 0 | 0 |
| SU1 | SdfUnit | 2150 | 1382 | 0 | 768 | 197 | 2 | 0 | 0 |
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
| MU | Multiply_26 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 1571 | 1379 | 0 | 192 | 197 | 2 | 0 | 0 |
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
| MU | Multiply_22 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 1439 | 1375 | 0 | 64 | 197 | 2 | 0 | 0 |
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized4 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
| MU | Multiply_18 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_19 | 540 | 540 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU4 | SdfUnit__parameterized2 | 1436 | 1372 | 0 | 64 | 197 | 2 | 0 | 0 |
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized5 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized6 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
| MU | Multiply | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle | 538 | 538 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 40589 | 40589 | 0 | 0 | 24484 | 2 | 6 | 0 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3642 | 3642 | 0 | 0 | 1021 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 36975 | 36975 | 0 | 0 | 23463 | 2 | 6 | 0 |
| (u_mlkem) | mlkem_top | 2550 | 2550 | 0 | 0 | 4907 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 484 | 484 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2469 | 2469 | 0 | 0 | 3199 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_ct_bram | sd_bram_4 | 20 | 20 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_5 | 101 | 101 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_6 | 226 | 226 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5251 | 5251 | 0 | 0 | 1619 | 0 | 0 | 0 |
| u_ntt | ntt_core | 13498 | 13498 | 0 | 0 | 3354 | 0 | 0 | 0 |
| u_pmul | poly_mul_sync | 7392 | 7392 | 0 | 0 | 6314 | 0 | 0 | 0 |
| (u_pmul) | poly_mul_sync | 5013 | 5013 | 0 | 0 | 6314 | 0 | 0 | 0 |
| u_bc | basecase_mul | 2379 | 2379 | 0 | 0 | 0 | 0 | 0 | 0 |
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul_zeta | barrett_mul_10 | 130 | 130 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_sha3 | sha3_top_shared | 1983 | 1983 | 0 | 0 | 2388 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_prng_axi_slave | prng_axi_slave | 502 | 502 | 0 | 0 | 338 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 9974 | 9792 | 176 | 6 | 3208 | 0 | 0 | 0 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5758 | 5576 | 176 | 6 | 2440 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1823 | 1823 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 605 | 605 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 1218 | 1218 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 776 | 776 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+

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fpga/vivado_reports/impl_worst_setup_paths.rpt Normal file
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fpga/vivado_reports/synth_timing_summary.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:34:34 2026
| Host : fedora running 64-bit unknown
| Command : report_timing_summary -file ./vivado_reports/synth_timing_summary.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
---------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 23490 register/latch pins with no clock driven by root clock pin: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 69061 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 38 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 40 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
2.111 0.000 0 43229 0.011 0.000 0 43229 7.000 0.000 0 17485
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk {0.000 10.000} 20.000 50.000
clkfbout_clk_pll {0.000 10.000} 20.000 50.000
cpu_clk {0.000 15.161} 30.323 32.979
sys_clk {0.000 10.000} 20.000 50.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk 7.000 0.000 0 1
clkfbout_clk_pll 17.845 0.000 0 3
cpu_clk 6.897 0.000 0 17197 0.011 0.000 0 17197 13.911 0.000 0 6486
sys_clk 2.111 0.000 0 23819 0.011 0.000 0 23819 8.750 0.000 0 10995
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** cpu_clk cpu_clk 27.780 0.000 0 67 0.676 0.000 0 67
**async_default** sys_clk sys_clk 17.299 0.000 0 2146 0.679 0.000 0 2146
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: clk
To Clock: clk
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clk }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: clkfbout_clk_pll
To Clock: clkfbout_clk_pll
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clkfbout_clk_pll
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 20.000 17.845 pll_clk.u_clk_pll/inst/clkf_buf/I
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: cpu_clk
To Clock: cpu_clk
Setup : 0 Failing Endpoints, Worst Slack 6.897ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 6.897ns (required time - arrival time)
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[25]/C
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Path Group: cpu_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
Data Path Delay: 23.236ns (logic 6.978ns (30.031%) route 16.258ns (69.969%))
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.918ns = ( 27.404 - 30.323 )
Source Clock Delay (SCD): -3.241ns
Clock Pessimism Removal (CPR): -0.468ns
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.130ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.584 -3.241 u_cpu/addr_trans/cpu_clk
FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[25]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.456 -2.785 r u_cpu/addr_trans/data_vaddr_buffer_reg[25]/Q
net (fo=65, unplaced) 1.054 -1.731 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[13]
LUT6 (Prop_lut6_I0_O) 0.295 -1.436 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_105/O
net (fo=1, unplaced) 0.000 -1.436 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_105_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 -0.886 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_30/CO[3]
net (fo=1, unplaced) 0.900 0.014 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_30_n_0
LUT6 (Prop_lut6_I3_O) 0.124 0.138 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_8/O
net (fo=4, unplaced) 0.926 1.064 u_cpu/addr_trans/tlb_entry/match1[31]
LUT4 (Prop_lut4_I1_O) 0.150 1.214 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
net (fo=2, unplaced) 0.460 1.674 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
LUT5 (Prop_lut5_I0_O) 0.118 1.792 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
net (fo=2, unplaced) 0.460 2.252 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
LUT6 (Prop_lut6_I0_O) 0.124 2.376 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
net (fo=89, unplaced) 0.571 2.947 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
MUXF7 (Prop_muxf7_S_O) 0.296 3.243 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
net (fo=1, unplaced) 0.000 3.243 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
MUXF8 (Prop_muxf8_I0_O) 0.104 3.347 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
net (fo=1, unplaced) 0.717 4.064 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
LUT5 (Prop_lut5_I0_O) 0.319 4.383 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
net (fo=1, unplaced) 0.449 4.832 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
LUT6 (Prop_lut6_I5_O) 0.124 4.956 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
net (fo=1, unplaced) 0.449 5.405 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
LUT6 (Prop_lut6_I5_O) 0.124 5.529 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
net (fo=10, unplaced) 0.492 6.021 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
LUT6 (Prop_lut6_I3_O) 0.124 6.145 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[4]_i_1__0/O
net (fo=6, unplaced) 0.934 7.079 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[16]
LUT6 (Prop_lut6_I0_O) 0.124 7.203 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
net (fo=1, unplaced) 0.000 7.203 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 7.753 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
net (fo=1, unplaced) 0.009 7.762 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
CARRY4 (Prop_carry4_CI_CO[2])
0.250 8.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
net (fo=5, unplaced) 0.480 8.492 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
LUT3 (Prop_lut3_I0_O) 0.310 8.802 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
net (fo=32, unplaced) 0.520 9.322 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
LUT6 (Prop_lut6_I5_O) 0.124 9.446 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O
net (fo=3, unplaced) 0.920 10.366 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22]
LUT6 (Prop_lut6_I1_O) 0.124 10.490 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
net (fo=3, unplaced) 0.467 10.957 u_cpu/mem_stage/p_5_in6_in[0]
LUT4 (Prop_lut4_I0_O) 0.118 11.075 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O
net (fo=8, unplaced) 0.487 11.562 u_cpu/u_div/ms_to_ws_bus_r_reg[40]
LUT5 (Prop_lut5_I4_O) 0.124 11.686 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O
net (fo=1, unplaced) 0.449 12.135 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40]
LUT4 (Prop_lut4_I2_O) 0.124 12.259 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O
net (fo=4, unplaced) 0.473 12.732 u_cpu/id_stage/ms_to_ds_forward_bus[8]
LUT5 (Prop_lut5_I2_O) 0.124 12.856 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O
net (fo=1, unplaced) 0.000 12.856 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 13.406 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
net (fo=1, unplaced) 0.000 13.406 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
CARRY4 (Prop_carry4_CI_O[1])
0.348 13.754 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
net (fo=1, unplaced) 0.611 14.365 u_cpu/id_stage/rd_csr_addr0[12]
LUT5 (Prop_lut5_I0_O) 0.332 14.697 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
net (fo=1, unplaced) 0.449 15.146 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
LUT5 (Prop_lut5_I1_O) 0.124 15.270 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
net (fo=3, unplaced) 0.467 15.737 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
LUT4 (Prop_lut4_I3_O) 0.124 15.861 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
net (fo=7, unplaced) 0.484 16.345 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
LUT6 (Prop_lut6_I5_O) 0.124 16.469 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
net (fo=19, unplaced) 0.508 16.977 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
LUT5 (Prop_lut5_I4_O) 0.124 17.101 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_24/O
net (fo=20, unplaced) 0.509 17.610 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_10
LUT4 (Prop_lut4_I2_O) 0.124 17.734 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_7/O
net (fo=1, unplaced) 1.111 18.845 u_cpu/id_stage/ds_to_es_bus_r[180]_i_7_n_0
LUT6 (Prop_lut6_I0_O) 0.124 18.969 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/O
net (fo=1, unplaced) 0.902 19.871 u_cpu/id_stage/ds_to_es_bus_r[180]_i_2_n_0
LUT6 (Prop_lut6_I1_O) 0.124 19.995 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O
net (fo=1, unplaced) 0.000 19.995 u_cpu/exe_stage/ds_to_es_bus[130]
FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 30.323 30.323 r
K21 0.000 30.323 r clk (IN)
net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.439 32.154 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-6.040 26.114 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.760 26.874 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.091 26.965 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.439 27.404 u_cpu/exe_stage/cpu_clk
FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C
clock pessimism -0.468 26.936
clock uncertainty -0.074 26.862
FDRE (Setup_fdre_C_D) 0.029 26.891 u_cpu/exe_stage/ds_to_es_bus_r_reg[180]
-------------------------------------------------------------------
required time 26.891
arrival time -19.995
-------------------------------------------------------------------
slack 6.897
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.011ns (arrival time - required time)
Source: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Path Group: cpu_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.650ns
Source Clock Delay (SCD): -0.978ns
Clock Pessimism Removal (CPR): 0.183ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0[0]
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
clock pessimism -0.183 -0.833
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]
-------------------------------------------------------------------
required time 0.763
arrival time -0.752
-------------------------------------------------------------------
slack 0.011
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: cpu_clk
Waveform(ns): { 0.000 15.161 }
Period(ns): 30.323
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: sys_clk
To Clock: sys_clk
Setup : 0 Failing Endpoints, Worst Slack 2.111ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.111ns (required time - arrival time)
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_matmul_axi_slave/crc_reg_reg[18]/D
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: sys_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
Data Path Delay: 17.702ns (logic 4.444ns (25.105%) route 13.258ns (74.895%))
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT5=5 LUT6=8)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
Source Clock Delay (SCD): -3.025ns
Clock Pessimism Removal (CPR): -0.468ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.122ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
CARRY4 (Prop_carry4_CI_O[1])
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
CARRY4 (Prop_carry4_S[1]_O[3])
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
net (fo=7, unplaced) 1.146 14.553 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
LUT6 (Prop_lut6_I1_O) 0.124 14.677 r u_matmul_axi_slave/crc_reg[18]_i_1/O
net (fo=1, unplaced) 0.000 14.677 u_matmul_axi_slave/crc32_word_next1_return[18]
FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 20.000 20.000 r
K21 0.000 20.000 r clk (IN)
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C
clock pessimism -0.468 16.830
clock uncertainty -0.071 16.759
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[18]
-------------------------------------------------------------------
required time 16.788
arrival time -14.677
-------------------------------------------------------------------
slack 2.111
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.011ns (arrival time - required time)
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: sys_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.555ns
Source Clock Delay (SCD): -0.882ns
Clock Pessimism Removal (CPR): 0.183ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0]
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
clock pessimism -0.183 -0.737
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
-------------------------------------------------------------------
required time 0.667
arrival time -0.657
-------------------------------------------------------------------
slack 0.011
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: sys_clk
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK
Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: cpu_clk
To Clock: cpu_clk
Setup : 0 Failing Endpoints, Worst Slack 27.780ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.676ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 27.780ns (required time - arrival time)
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
(recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
Data Path Delay: 1.915ns (logic 0.751ns (39.217%) route 1.164ns (60.783%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.918ns = ( 27.404 - 30.323 )
Source Clock Delay (SCD): -3.241ns
Clock Pessimism Removal (CPR): -0.468ns
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.130ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.584 -3.241 pll_clk.u_rst_cpu/cpu_clk
FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.456 -2.785 r pll_clk.u_rst_cpu/delay_reg[1]/Q
net (fo=1, unplaced) 0.311 -2.474 pll_clk.u_rst_cpu/cpu_resetn
LUT1 (Prop_lut1_I0_O) 0.295 -2.179 f pll_clk.u_rst_cpu/reset_i_1/O
net (fo=40, unplaced) 0.853 -1.326 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 30.323 30.323 r
K21 0.000 30.323 r clk (IN)
net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.439 32.154 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-6.040 26.114 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.760 26.874 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.091 26.965 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.439 27.404 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
clock pessimism -0.468 26.936
clock uncertainty -0.074 26.862
FDCE (Recov_fdce_C_CLR) -0.409 26.453 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]
-------------------------------------------------------------------
required time 26.453
arrival time 1.326
-------------------------------------------------------------------
slack 27.780
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.676ns (arrival time - required time)
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
Data Path Delay: 0.727ns (logic 0.239ns (32.888%) route 0.488ns (67.112%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.650ns
Source Clock Delay (SCD): -0.978ns
Clock Pessimism Removal (CPR): 0.183ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
net (fo=1, unplaced) 0.131 -0.706 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
LUT1 (Prop_lut1_I0_O) 0.098 -0.608 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
net (fo=30, unplaced) 0.357 -0.251 u_Axi_CDC/bFifo/buffers_1_reg
FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/bFifo/cpu_clk
FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C
clock pessimism -0.183 -0.833
FDCE (Remov_fdce_C_CLR) -0.094 -0.927 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg
-------------------------------------------------------------------
required time 0.927
arrival time -0.251
-------------------------------------------------------------------
slack 0.676
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: sys_clk
To Clock: sys_clk
Setup : 0 Failing Endpoints, Worst Slack 17.299ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.679ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 17.299ns (required time - arrival time)
Source: pll_clk.u_rst_sys/delay_reg[1]/C
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/CLR
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
Data Path Delay: 2.076ns (logic 0.745ns (35.886%) route 1.331ns (64.114%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
Source Clock Delay (SCD): -3.025ns
Clock Pessimism Removal (CPR): -0.468ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.122ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.800 -3.025 pll_clk.u_rst_sys/sys_clk
FDCE r pll_clk.u_rst_sys/delay_reg[1]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.456 -2.569 r pll_clk.u_rst_sys/delay_reg[1]/Q
net (fo=119, unplaced) 0.415 -2.154 pll_clk.u_rst_sys/Q[0]
LUT1 (Prop_lut1_I0_O) 0.289 -1.865 f pll_clk.u_rst_sys/r_wb[7]_i_4/O
net (fo=28767, unplaced) 0.916 -0.949 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/p_0_in
FDCE f u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/CLR
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 20.000 20.000 r
K21 0.000 20.000 r clk (IN)
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.655 17.297 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/sys_clk
FDCE r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/C
clock pessimism -0.468 16.830
clock uncertainty -0.071 16.759
FDCE (Recov_fdce_C_CLR) -0.409 16.350 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg
-------------------------------------------------------------------
required time 16.350
arrival time 0.949
-------------------------------------------------------------------
slack 17.299
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.679ns (arrival time - required time)
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/CLR
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
Data Path Delay: 0.730ns (logic 0.239ns (32.718%) route 0.491ns (67.282%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.555ns
Source Clock Delay (SCD): -0.882ns
Clock Pessimism Removal (CPR): 0.183ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
net (fo=1, unplaced) 0.131 -0.610 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
LUT1 (Prop_lut1_I0_O) 0.098 -0.512 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
net (fo=43, unplaced) 0.360 -0.152 u_Axi_CDC/arFifo/buffers_0_reg[2]
FDCE f u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/CLR
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/sys_clk
FDCE r u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/C
clock pessimism -0.183 -0.737
FDCE (Remov_fdce_C_CLR) -0.094 -0.831 u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg
-------------------------------------------------------------------
required time 0.831
arrival time -0.152
-------------------------------------------------------------------
slack 0.679

203
fpga/vivado_reports/synth_utilization.rpt Normal file
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@@ -0,0 +1,203 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:34:12 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -file ./vivado_reports/synth_utilization.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs* | 74980 | 0 | 134600 | 55.71 |
| LUT as Logic | 73234 | 0 | 134600 | 54.41 |
| LUT as Memory | 1746 | 0 | 46200 | 3.78 |
| LUT as Distributed RAM | 652 | 0 | | |
| LUT as Shift Register | 1094 | 0 | | |
| Slice Registers | 38603 | 0 | 269200 | 14.34 |
| Register as Flip Flop | 38603 | 0 | 269200 | 14.34 |
| Register as Latch | 0 | 0 | 269200 | 0.00 |
| F7 Muxes | 4263 | 0 | 67300 | 6.33 |
| F8 Muxes | 1403 | 0 | 33650 | 4.17 |
+----------------------------+-------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 101 | Yes | - | Set |
| 25523 | Yes | - | Reset |
| 134 | Yes | Set | - |
| 12845 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
| RAMB36E1 only | 10 | | | |
| RAMB18 | 31 | 0 | 730 | 4.25 |
| RAMB18E1 only | 31 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 202 | 202 | 400 | 50.50 |
| IOB Master Pads | 97 | | | |
| IOB Slave Pads | 102 | | | |
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
| PHASER_REF | 0 | 0 | 10 | 0.00 |
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
| IN_FIFO | 0 | 0 | 40 | 0.00 |
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
| IBUFDS | 0 | 0 | 384 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
| ILOGIC | 0 | 0 | 400 | 0.00 |
| OLOGIC | 0 | 0 | 400 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
| BUFIO | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
| BUFMRCE | 0 | 0 | 20 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 40 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| LUT6 | 36042 | LUT |
| FDCE | 25523 | Flop & Latch |
| LUT5 | 16007 | LUT |
| LUT3 | 13060 | LUT |
| FDRE | 12845 | Flop & Latch |
| LUT4 | 11977 | LUT |
| LUT2 | 9006 | LUT |
| MUXF7 | 4263 | MuxFx |
| CARRY4 | 3590 | CarryLogic |
| MUXF8 | 1403 | MuxFx |
| SRLC32E | 992 | Distributed Memory |
| RAMD32 | 892 | Distributed Memory |
| LUT1 | 816 | LUT |
| RAMS32 | 272 | Distributed Memory |
| FDSE | 134 | Flop & Latch |
| IBUF | 104 | IO |
| SRL16E | 102 | Distributed Memory |
| FDPE | 101 | Flop & Latch |
| OBUF | 98 | IO |
| OBUFT | 66 | IO |
| RAMD64E | 32 | Distributed Memory |
| RAMB18E1 | 31 | Block Memory |
| RAMB36E1 | 10 | Block Memory |
| BUFG | 4 | Clock |
| PLLE2_ADV | 1 | Clock |
+-----------+-------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
| clk_pll | 1 |
+----------+------+

255
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:34:18 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports/synth_utilization_hier.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Utilization by Hierarchy
1. Utilization by Hierarchy
---------------------------
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| soc_top | (top) | 74980 | 73234 | 652 | 1094 | 38603 | 10 | 31 | 0 |
| (soc_top) | (top) | 2116 | 2060 | 56 | 0 | 4 | 0 | 0 | 0 |
| pll_clk.u_clk_pll | clk_pll | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll_clk_pll_clk_wiz | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 519 | 519 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 61 | 61 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 25 | 25 | 0 | 0 | 14 | 0 | 0 | 0 |
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 505 | 377 | 128 | 0 | 309 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 262 | 226 | 36 | 0 | 73 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 256 | 220 | 36 | 0 | 61 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 112 | 76 | 36 | 0 | 75 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 105 | 69 | 36 | 0 | 61 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 16 | 16 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 9 | 9 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 69 | 41 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1355 | 1355 | 0 | 0 | 161 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 648 | 648 | 0 | 0 | 81 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 707 | 707 | 0 | 0 | 80 | 0 | 0 | 0 |
| u_axi_dvi | axi_dvi | 285 | 285 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 693 | 677 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 121 | 121 | 0 | 0 | 155 | 0 | 0 | 0 |
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
| receiver | uart_receiver | 231 | 223 | 8 | 0 | 124 | 0 | 0 | 0 |
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
| fifo_rx | uart_rfifo | 163 | 155 | 8 | 0 | 70 | 0 | 0 | 0 |
| (fifo_rx) | uart_rfifo | 144 | 144 | 0 | 0 | 62 | 0 | 0 | 0 |
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 86 | 78 | 8 | 0 | 56 | 0 | 0 | 0 |
| (transmitter) | uart_transmitter | 42 | 42 | 0 | 0 | 35 | 0 | 0 | 0 |
| fifo_tx | uart_tfifo | 44 | 36 | 8 | 0 | 21 | 0 | 0 | 0 |
| (fifo_tx) | uart_tfifo | 25 | 25 | 0 | 0 | 13 | 0 | 0 | 0 |
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_confreg | confreg | 391 | 391 | 0 | 0 | 460 | 0 | 0 | 0 |
| (u_confreg) | confreg | 231 | 231 | 0 | 0 | 383 | 0 | 0 | 0 |
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
| u_cpu | core_top | 8656 | 8380 | 276 | 0 | 5591 | 0 | 20 | 0 |
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2264 | 2100 | 164 | 0 | 1244 | 0 | 0 | 0 |
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2264 | 2100 | 164 | 0 | 1204 | 0 | 0 | 0 |
| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 |
| btb | btb | 1064 | 984 | 80 | 0 | 1611 | 0 | 0 | 0 |
| (btb) | btb | 1061 | 981 | 80 | 0 | 1611 | 0 | 0 | 0 |
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
| dcache | dcache | 569 | 537 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 92 | 60 | 32 | 0 | 138 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_46 | 46 | 46 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 650 | 650 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
| icache | icache | 239 | 239 | 0 | 0 | 55 | 0 | 10 | 0 |
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
| id_stage | id_stage | 1058 | 1058 | 0 | 0 | 108 | 0 | 0 | 0 |
| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 |
| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
| u_div | div | 143 | 143 | 0 | 0 | 107 | 0 | 0 | 0 |
| u_mul | mul | 943 | 943 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 685 | 685 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 48074 | 46986 | 0 | 1088 | 25915 | 10 | 10 | 0 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 6966 | 5878 | 0 | 1088 | 1087 | 8 | 4 | 0 |
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
| u_FFT | FFT | 6855 | 5767 | 0 | 1088 | 983 | 8 | 0 | 0 |
| SU1 | SdfUnit | 2150 | 1382 | 0 | 768 | 197 | 2 | 0 | 0 |
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
| MU | Multiply_26 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 1571 | 1379 | 0 | 192 | 197 | 2 | 0 | 0 |
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
| MU | Multiply_22 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 1439 | 1375 | 0 | 64 | 197 | 2 | 0 | 0 |
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized4 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
| MU | Multiply_18 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_19 | 540 | 540 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU4 | SdfUnit__parameterized2 | 1436 | 1372 | 0 | 64 | 197 | 2 | 0 | 0 |
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized5 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized6 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
| MU | Multiply | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle | 538 | 538 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 40589 | 40589 | 0 | 0 | 24484 | 2 | 6 | 0 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3642 | 3642 | 0 | 0 | 1021 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 36975 | 36975 | 0 | 0 | 23463 | 2 | 6 | 0 |
| (u_mlkem) | mlkem_top | 2550 | 2550 | 0 | 0 | 4907 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 484 | 484 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2469 | 2469 | 0 | 0 | 3199 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_ct_bram | sd_bram_4 | 20 | 20 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_5 | 101 | 101 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_6 | 226 | 226 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5251 | 5251 | 0 | 0 | 1619 | 0 | 0 | 0 |
| u_ntt | ntt_core | 13498 | 13498 | 0 | 0 | 3354 | 0 | 0 | 0 |
| u_pmul | poly_mul_sync | 7392 | 7392 | 0 | 0 | 6314 | 0 | 0 | 0 |
| (u_pmul) | poly_mul_sync | 5013 | 5013 | 0 | 0 | 6314 | 0 | 0 | 0 |
| u_bc | basecase_mul | 2379 | 2379 | 0 | 0 | 0 | 0 | 0 | 0 |
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul_zeta | barrett_mul_10 | 130 | 130 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_sha3 | sha3_top_shared | 1983 | 1983 | 0 | 0 | 2388 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_prng_axi_slave | prng_axi_slave | 502 | 502 | 0 | 0 | 338 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 9974 | 9792 | 176 | 6 | 3208 | 0 | 0 | 0 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5758 | 5576 | 176 | 6 | 2440 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1823 | 1823 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 605 | 605 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 1218 | 1218 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 776 | 776 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+