FallenSigh a369a421b7 feat(phase3): implement storage BRAMs and Compress/Decompress ...

Phase 3.1 + 3.3:
- sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM)
- s_bram.v: single-port RAM (rd_en/wr_en, write priority)
- comp_decomp_sync.v: streaming compress/decompress with round-half-up

Verified: storage 5/5, comp_decomp 60/60 all PASS

2026-06-24 23:28:06 +08:00

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