FallenSigh
92dafc9696
Add (* use_dsp = "no" *) to all modules containing multiplication operators to force LUT-based multiplication instead of DSP inference: - barrett_mul.v (3 multipliers x 7 instances = 21 ops) - comp_decomp_sync.v, sample_ntt_sync*.v, mlkem_top.v Also fix duplicate wire declaration of ct_bytes_rt in mlkem_top.v.
76 lines
2.5 KiB
Verilog
76 lines
2.5 KiB
Verilog
// comp_decomp_sync.v - ML-KEM coefficient compression/decompression
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//
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// Streaming: one coefficient per cycle through pipeline_reg.
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// mode=0: compress — round((2^d * x) / Q) mod 2^d
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// mode=1: decompress — round((Q * x) / 2^d) mod Q
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// Uses round-half-up (round(2.5)=3, round(3.5)=4).
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// Integer arithmetic:
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// compress: (x * 2^d + Q/2) / Q, lower d bits as result
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// decompress: (x * Q + 2^(d-1)) / 2^d, result (always < Q)
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`include "sync_rtl/common/defines.vh"
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(* use_dsp = "no" *)
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module comp_decomp_sync (
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input clk,
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input rst_n,
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input [11:0] coeff_in,
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input [4:0] d,
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input mode, // 0=compress, 1=decompress
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input valid_i,
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output ready_o,
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output [11:0] coeff_out,
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output valid_o,
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input ready_i
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);
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// 2^d for d in {4,5,10,11}; fits in 12 bits (max 2048)
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wire [11:0] two_pow_d;
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assign two_pow_d = 12'd1 << d;
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// Product: 12-bit * 12-bit = max 2048*3328 = 6,815,744 → 23 bits (use 24)
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wire [23:0] product;
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// compress: x * 2^d; decompress: x * Q
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assign product = mode ? {12'b0, coeff_in} * {12'b0, 12'(`Q)}
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: {12'b0, coeff_in} * {12'b0, two_pow_d};
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// Rounding offset: compress→Q/2=1664; decompress→2^(d-1)
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wire [11:0] round_off;
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assign round_off = mode ? (two_pow_d >> 1) : 12'd1664;
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// Dividend = product + round_off (max ~ 6,817,408 fits in 24 bits)
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wire [23:0] dividend;
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assign dividend = product + {12'b0, round_off};
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// Divisor: compress→Q=3329; decompress→2^d
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wire [11:0] divisor;
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assign divisor = mode ? two_pow_d : 12'(`Q);
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// Integer division (both ops positive → floor)
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// Quotient is computed as 24b (widest operand) but fits in 12b
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/* verilator lint_off WIDTHTRUNC */
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wire [11:0] div_result;
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assign div_result = dividend / {12'b0, divisor};
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/* verilator lint_on WIDTHTRUNC */
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// Final modular reduction
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// compress: lower d bits (mask with 2^d - 1)
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// decompress: result < Q always, but apply mod Q for safety
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wire [11:0] mod_result;
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assign mod_result = mode ? (div_result % 12'(`Q)) : (div_result & (two_pow_d - 1'b1));
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// Pipeline through valid/ready stage
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pipeline_reg #(.DW(12)) u_pipe (
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.clk (clk),
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.rst_n (rst_n),
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.data_i (mod_result),
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.valid_i(valid_i),
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.ready_o(ready_o),
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.data_o (coeff_out),
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.valid_o(valid_o),
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.ready_i(ready_i)
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);
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endmodule
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