FallenSigh
d4c3fc86fc
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
63 lines
1.9 KiB
Tcl
63 lines
1.9 KiB
Tcl
# xsim_run.tcl - Vivado xsim compilation and simulation script for NTT
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#
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# Compiles all NTT RTL sources plus testbench and runs simulation.
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# Run from the project root: ~/Dev/mlkem/
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#
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# Prerequisites:
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# source /opt/Xilinx/Vivado/2019.2/settings64.sh
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#
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# Usage examples:
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# # Run ntt_core testbench
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# xsim ntt_core_sim -R
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#
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# # Step-by-step:
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# vivado -mode batch -source xsim_run.tcl
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# ================================================================
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# Configuration
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# ================================================================
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set SRC_DIR sync_rtl/ntt
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set TB_DIR sync_rtl/ntt/TB
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# ================================================================
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# Step 1: Compile all source files (xvlog)
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# ================================================================
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puts "=== Compiling RTL sources ==="
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# Barrett modular multiplier (combinational)
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xvlog -sv ${SRC_DIR}/barrett_mul.v
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# Zeta ROM (combinational)
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xvlog -sv ${SRC_DIR}/zeta_rom.v
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# Butterfly unit (combinational, instantiates barrett_mul)
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xvlog -sv ${SRC_DIR}/butterfly_unit.v
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# NTT core (FSM-based, instantiates butterfly_unit + zeta_rom + barrett_mul)
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xvlog -sv ${SRC_DIR}/ntt_core.v
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# ================================================================
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# Step 2: Compile testbench
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# ================================================================
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puts "=== Compiling testbench ==="
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# File-based vector testbench for ntt_core
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xvlog -sv ${TB_DIR}/tb_ntt_core_xsim.v
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# ================================================================
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# Step 3: Elaborate (xelab)
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# ================================================================
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puts "=== Elaborating snapshot ==="
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xelab tb_ntt_core_xsim -s ntt_core_sim
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# ================================================================
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# Step 4: Run simulation
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# ================================================================
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puts ""
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puts "=== Running ntt_core test ==="
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xsim ntt_core_sim -R
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puts ""
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puts "=== Simulation complete ==="
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