FallenSigh
d4c3fc86fc
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
61 lines
2.1 KiB
Tcl
61 lines
2.1 KiB
Tcl
# xsim_run.tcl - Vivado xsim compilation and simulation script for comp_decomp_sync
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#
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# Compiles comp_decomp_sync RTL + dependencies + testbench and runs simulation.
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# Run from the project root: ~/Dev/mlkem/
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#
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# Prerequisites:
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# source /opt/Xilinx/Vivado/2019.2/settings64.sh
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#
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# Usage examples:
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# # Step-by-step (from Tcl):
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# xsim -runall xsim_run.tcl
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#
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# # Or via Vivado batch mode:
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# vivado -mode batch -source xsim_run.tcl
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#
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# # Or manually:
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# xvlog -sv sync_rtl/common/pipeline_reg.v sync_rtl/comp_decomp/comp_decomp_sync.v sync_rtl/comp_decomp/TB/tb_comp_decomp_xsim.v
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# xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
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# xsim tb_comp_decomp_xsim -R
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# ================================================================
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# Configuration
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# ================================================================
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set RTL_DIR sync_rtl
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set DUT_DIR sync_rtl/comp_decomp
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set TB_DIR sync_rtl/comp_decomp/TB
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# ================================================================
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# Step 1: Compile all source files (xvlog)
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# ================================================================
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puts "=== Compiling RTL sources for comp_decomp_sync ==="
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# Common dependency (pipeline register)
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xvlog -sv -include_dirs . ${RTL_DIR}/common/pipeline_reg.v
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# DUT (comp_decomp_sync) — uses `include "sync_rtl/common/defines.vh"
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xvlog -sv -include_dirs . ${DUT_DIR}/comp_decomp_sync.v
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# ================================================================
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# Step 2: Compile testbench
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# ================================================================
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puts "=== Compiling testbench ==="
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xvlog -sv ${TB_DIR}/tb_comp_decomp_xsim.v
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# ================================================================
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# Step 3: Elaborate snapshot (xelab)
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# ================================================================
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puts "=== Elaborating snapshot ==="
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xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
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# ================================================================
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# Step 4: Run simulation
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# ================================================================
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puts "=== Running comp_decomp_sync XSIM test ==="
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xsim tb_comp_decomp_xsim -R
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puts ""
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puts "=== Simulation complete ==="
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