FallenSigh
a38c41a1f5
Final bank promoted to sd_bram (the busiest: 5 read sites, 2 write sites). Read port phase-muxed: ST_N load / ST_M load (pm_b s_hat[j]) vs accumulate (e_hat, selected by m_loading) / ST_E dk-half / dbg. Write port combinational: ST_C CBD store vs ST_N NTT writeback (disjoint states). All explicit consumer read registers (n_rd_data, pm_b_rd, m_eacc_rd, e_se_rd) collapsed into the sd_bram internal read register; m_acc_src and e_rd_coeff now select between two registered sd_bram outputs (same 1-cycle latency). mlkem_top now contains ZERO behavioural RAM arrays: all coefficient storage is 3 sd_bram banks (a/se/t) + ek/dkp byte buffers = 5 sd_bram instances total, each inferring BRAM (ASIC: compiled SRAM). 11/11 KAT PASS, byte-exact.
1012 lines
47 KiB
Verilog
1012 lines
47 KiB
Verilog
// mlkem_top.v - ML-KEM KeyGen top-level integration. Runtime-selectable
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// parameter set via k_i: k=2 (ML-KEM-512, eta1=3), k=3 (768), k=4 (1024).
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// Storage is sized for KMAX (worst case = ML-KEM-1024); k_i picks the
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// active sub-range at start_i.
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//
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// Streaming valid/ready interface. Given seeds d and z, computes the
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// ML-KEM key pair per FIPS 203 Algorithm 16 (KeyGen_internal):
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// (rho,sigma) = G(d || K)
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// A_hat[i][j] = SampleNTT(rho || j || i) i,j in 0..K-1
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// s[i] = CBD3(PRF(sigma, i)), e[i] = CBD3(PRF(sigma, K+i))
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// s_hat[i] = NTT(s[i]); e_hat[i] = NTT(e[i])
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// t_hat[i] = e_hat[i] + sum_j A_hat[i][j] o s_hat[j]
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// ek = byteEncode12(t_hat[0..K-1]) || rho
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// dk = byteEncode12(s_hat[0..K-1]) || ek || H(ek) || z
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//
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// Built incrementally and verified stage-by-stage against ml-kem-r golden
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// vectors (test_framework/modules/mlkem_keygen/golden) and NIST KAT.
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//
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// Uses independent (verified) leaf modules, each with its own keccak_core:
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// sha3_top, sample_ntt_sync, sample_cbd_sync, ntt_core, poly_mul_sync,
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// mod_add_sync. No shared-keccak arbiter.
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`include "sync_rtl/common/defines.vh"
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module mlkem_top #(
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parameter KMAX = 4 // storage sizing (worst case = ML-KEM-1024)
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) (
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input clk,
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input rst_n,
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input [2:0] k_i, // RUNTIME ML-KEM param: 2=512, 3=768, 4=1024
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input [255:0] d_i, // KeyGen seed d (byte 0 in d_i[7:0])
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input [255:0] z_i, // implicit-rejection seed z
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input start_i, // pulse to begin KeyGen
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output busy_o, // high while running
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output done_o, // pulse when ek/dk ready
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// Debug readback tap: read one stored coefficient by (poly slot, index).
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// Lets stage TBs verify intermediates without wide buses.
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input [3:0] dbg_slot_i, // poly slot (see localparams below)
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input [7:0] dbg_idx_i, // coefficient index 0..255
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output [11:0] dbg_coeff_o,
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// Debug byte readback: ek (sel=0, 0..799) / dk_pke (sel=1, 0..767)
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input dbg_byte_sel_i,
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input [10:0] dbg_byte_idx_i,
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output [7:0] dbg_byte_o,
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// Debug full-dk readback: dk = dk_pke(768) || ek(800) || H(ek)(32) || z(32)
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// = 1632 bytes. Index 0..1631.
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input [11:0] dbg_dk_idx_i,
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output [7:0] dbg_dk_o,
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// Debug taps for hash outputs
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output [255:0] dbg_rho_o,
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output [255:0] dbg_sigma_o
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);
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localparam Q = `Q; // 3329
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// Runtime ML-KEM parameter, captured at start_i.
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reg [2:0] k_r;
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// FIPS 203: eta1 = 3 for ML-KEM-512 (k=2), else 2 (k=3/4).
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wire [1:0] eta1_rt = (k_r == 3'd2) ? 2'd3 : 2'd2;
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// Runtime-derived sizes (k_r in {2,3,4}). Small multiplies are cheap.
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wire [5:0] kk_rt = k_r * k_r; // 4/9/16
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wire [5:0] slot_s_rt = kk_rt; // s_hat base slot
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wire [5:0] slot_e_rt = kk_rt + k_r; // e_hat base slot
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wire [5:0] slot_t_rt = kk_rt + {1'b0, k_r} + {1'b0, k_r}; // t_hat base = kk+2k
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wire [11:0] ek_bytes_rt = 12'd384 * {9'b0, k_r} + 12'd32; // 800/1184/1568
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wire [11:0] dk_bytes_rt = 12'd384 * {9'b0, k_r}; // 768/1152/1536
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// H(ek) block count = ceil((ek_bytes+1)/136): 6/9/12 for k=2/3/4 (table)
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wire [3:0] h_nblk_rt = (k_r == 3'd2) ? 4'd6 : (k_r == 3'd3) ? 4'd9 : 4'd12;
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wire [11:0] h_last_rt = {6'b0, h_nblk_rt} * 12'd136 - 12'd1; // final padded byte index
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// ================================================================
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// Polynomial storage, sized for KMAX (worst case). Runtime k uses a
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// sub-range. Slot layout (each slot = 256 coeffs):
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// A_hat[i][j] : slots 0 .. k*k-1 at index i*k + j
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// s_hat[i] : slots slot_s_rt .. +k-1
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// e_hat[i] : slots slot_e_rt .. +k-1
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// t_hat[i] : slots slot_t_rt .. +k-1
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// NUM_SLOTS = KMAX*KMAX + 3*KMAX = 28 for KMAX=4.
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// ================================================================
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localparam NUM_SLOTS = KMAX*KMAX + 3*KMAX;
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localparam SAW = 5; // slot-address width (>=clog2(28))
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// ================================================================
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// Coefficient storage as 3 banks (Phase 2). Was one async-read reg
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// array polymem[0:28*256-1]; split by polynomial so each becomes a
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// registered-read sd_bram (infers BRAM / ASIC SRAM) in the final step.
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// bank_a : A_hat[i][j] slots 0..K^2-1 -> D=KMAX*KMAX*256=4096
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// bank_se: s_hat||e_hat slots slot_s.. -> D=2*KMAX*256=2048 (rel 0..2K-1)
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// bank_t : t_hat[i] slots slot_t.. -> D=KMAX*256=1024 (rel 0..K-1)
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// Addresses are base-relative: bank index = abs_slot - base_slot.
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// Stage 2b (in progress): per-consumer registered read-ahead. Banks are
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// still async reg arrays here; converted consumers read via their own
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// 1-cycle pipeline reg (== sd_bram timing). Once every consumer of a
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// bank is registered, the array is replaced by an sd_bram with its read
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// port muxed across the (phase-disjoint) consumers.
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// ================================================================
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localparam PA_AW = 12; // bank_a addr width (4096)
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localparam PSE_AW = 11; // bank_se addr width (2048)
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localparam PT_AW = 10; // bank_t addr width (1024)
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// bank_a: A_hat. Reader = ST_M load (pm_a) + dbg. Writer = ST_A.
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// Read port muxed by phase; sd_bram's internal rd_addr_r register is the
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// 1-cycle read pipeline (replaces the explicit pm_a_rd reg). Write port is
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// driven combinationally (sd_bram registers the write at posedge, matching
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// the old reg-array nonblocking write timing).
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wire [PA_AW-1:0] ba_rd_addr;
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wire [11:0] ba_rd_data;
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wire ba_we;
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wire [PA_AW-1:0] ba_wa;
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wire [11:0] ba_wd;
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sd_bram #(.W(12), .D(1<<PA_AW), .A(PA_AW)) u_bank_a (
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.clk(clk), .rd_addr(ba_rd_addr), .rd_data(ba_rd_data),
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.wr_en(ba_we), .wr_addr(ba_wa), .wr_data(ba_wd)
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);
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// ST_A write: commit snt_coeff to A_hat[a_slot] the cycle it is accepted.
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assign ba_we = (st == ST_A) && a_busy && snt_vo && snt_ack;
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assign ba_wa = (a_slot*256 + a_widx) & ((1<<PA_AW)-1);
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assign ba_wd = snt_coeff;
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// bank_se: s_hat || e_hat. Readers = ST_N load, ST_M load (pm_b, s_hat[j]),
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// ST_M acc (e_hat, j==0), ST_E dk-half, dbg. Writers = ST_C (CBD), ST_N
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// writeback (NTT in place). All readers already registered; read port muxed
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// by phase (within ST_M, load vs accumulate never overlap). Write port
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// combinational (ST_C and ST_N are disjoint states).
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wire [PSE_AW-1:0] bse_rd_addr;
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wire [11:0] bse_rd_data;
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wire bse_we;
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wire [PSE_AW-1:0] bse_wa;
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wire [11:0] bse_wd;
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sd_bram #(.W(12), .D(1<<PSE_AW), .A(PSE_AW)) u_bank_se (
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.clk(clk), .rd_addr(bse_rd_addr), .rd_data(bse_rd_data),
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.wr_en(bse_we), .wr_addr(bse_wa), .wr_data(bse_wd)
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);
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// bank_t: t_hat. Readers = ST_M acc (j>0 running t_hat) + ST_E ek-half + dbg.
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// Writer = ST_M acc. Read port muxed by phase; sd_bram's rd_addr_r is the
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// 1-cycle read register. RMW is safe: the acc read addr leads the write
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// addr by 1 (m_oidx+1 vs m_oidx), so read/write never alias in a cycle and
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// sd_bram write-first == reg-array read-old. Write port combinational.
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wire [PT_AW-1:0] bt_rd_addr;
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wire [11:0] bt_rd_data;
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wire bt_we;
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wire [PT_AW-1:0] bt_wa;
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wire [11:0] bt_wd;
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sd_bram #(.W(12), .D(1<<PT_AW), .A(PT_AW)) u_bank_t (
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.clk(clk), .rd_addr(bt_rd_addr), .rd_data(bt_rd_data),
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.wr_en(bt_we), .wr_addr(bt_wa), .wr_data(bt_wd)
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);
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// ST_M accumulate write: t_hat[m_i][m_oidx] <= (acc + product) mod Q when pm_vo.
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assign bt_we = (st == ST_M) && pm_vo;
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assign bt_wa = (m_i*256 + m_oidx) & ((1<<PT_AW)-1);
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assign bt_wd = m_accq;
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// Debug readback (registered for timing)
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reg [11:0] dbg_coeff_r;
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// Route debug read by absolute slot range (not on the KAT correctness
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// path — TB reads ek/dk BRAMs only). A: 0..K^2-1; s/e: slot_s..slot_t-1;
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// t: slot_t.. Index within bank is (abs_slot-base)*256 + idx.
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wire [13:0] dbg_a_addr = dbg_slot_i*256 + dbg_idx_i;
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wire [13:0] dbg_se_addr = (dbg_slot_i - slot_s_rt)*256 + dbg_idx_i;
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wire [13:0] dbg_t_addr = (dbg_slot_i - slot_t_rt)*256 + dbg_idx_i;
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// bank_a read port: ST_M load drives pm_a_full; otherwise debug index.
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assign ba_rd_addr = (st == ST_M) ? pm_a_full[PA_AW-1:0] : dbg_a_addr[PA_AW-1:0];
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// bank_t read port: ST_M acc drives the t_hat accumulate addr; ST_E ek-half
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// drives the byteEncode addr; otherwise debug index.
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assign bt_rd_addr = (st == ST_M) ? m_tacc_full[PT_AW-1:0] :
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(st == ST_E) ? e_rd_full[PT_AW-1:0] :
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dbg_t_addr[PT_AW-1:0];
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// bank_se read port: ST_N load (s/e NTT), ST_M load (pm_b s_hat[j]) vs
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// accumulate (e_hat, mutually exclusive via m_loading), ST_E dk-half, dbg.
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assign bse_rd_addr = (st == ST_N) ? ntt_rd_full[PSE_AW-1:0] :
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(st == ST_M) ? (m_loading ? pm_b_full[PSE_AW-1:0]
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: m_eacc_full[PSE_AW-1:0]) :
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(st == ST_E) ? e_rd_full[PSE_AW-1:0] :
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dbg_se_addr[PSE_AW-1:0];
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// bank_se write port: ST_C CBD store (rel slot c_poly), ST_N NTT writeback
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// (rel slot n_slot). Disjoint states.
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assign bse_we = ((st == ST_C) && c_busy && cbd_vo && cbd_ack) ||
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((st == ST_N) && ntt_vo);
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assign bse_wa = (st == ST_N) ? ((n_slot*256 + n_widx) & ((1<<PSE_AW)-1))
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: ((c_poly*256 + c_widx) & ((1<<PSE_AW)-1));
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assign bse_wd = (st == ST_N) ? ntt_coeff : cbd_modq;
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always @(posedge clk) begin
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if (dbg_slot_i >= slot_t_rt) dbg_coeff_r <= bt_rd_data; // bank_t (sd_bram)
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else if (dbg_slot_i >= slot_s_rt) dbg_coeff_r <= bse_rd_data; // bank_se (sd_bram)
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else dbg_coeff_r <= ba_rd_data; // bank_a (sd_bram)
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end
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assign dbg_coeff_o = dbg_coeff_r;
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// ek and dk_pke byte memories sized for KMAX.
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localparam EK_MAX = 384*KMAX + 32; // 1568
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localparam DK_MAX = 384*KMAX; // 1536
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// ek / dk_pke byte storage in BRAM (sd_bram: 1R/1W, 1-cycle read latency).
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// Each single read port is shared time-disjointly: ST_H assemble reads ek
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// (in ST_H), debug readback reads ek/dk (in ST_DONE). Write port driven by
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// ST_E (1 byte/cycle) and the rho-tail copy.
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wire [10:0] ek_rd_addr, dkp_rd_addr;
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wire [7:0] ek_rd_data, dkp_rd_data;
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reg ek_we, dkp_we;
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reg [10:0] ek_wa, dkp_wa;
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reg [7:0] ek_wd, dkp_wd;
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sd_bram #(.W(8), .D(2048), .A(11)) u_ek_bram (
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.clk(clk),
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.rd_addr(ek_rd_addr), .rd_data(ek_rd_data),
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.wr_en(ek_we), .wr_addr(ek_wa), .wr_data(ek_wd)
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);
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sd_bram #(.W(8), .D(2048), .A(11)) u_dkp_bram (
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.clk(clk),
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.rd_addr(dkp_rd_addr), .rd_data(dkp_rd_data),
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.wr_en(dkp_we), .wr_addr(dkp_wa), .wr_data(dkp_wd)
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);
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// full dk = dk_pke(dk_bytes) || ek(ek_bytes) || H(ek)(32) || z(32)
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wire [11:0] dk_ek_end = dk_bytes_rt + ek_bytes_rt; // ek region end
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wire [11:0] dk_hek_end = dk_ek_end + 12'd32; // H(ek) region end
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// Debug-region selects for dk readback (combinational region decode).
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wire dbgdk_in_dkp = (dbg_dk_idx_i < dk_bytes_rt);
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wire dbgdk_in_ek = (dbg_dk_idx_i >= dk_bytes_rt) && (dbg_dk_idx_i < dk_ek_end);
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// Read-address muxes (declared here; depend on ST_H h_g defined below via
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// the function-free expression h_blk*136 + h_byte). See assigns after the
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// H-stage register declarations.
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// dbg_byte_o / dbg_dk_o are combinational taps over the (registered) BRAM
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// read data; net 1-cycle latency, well within the TB's 2-cycle read wait.
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assign dbg_byte_o = dbg_byte_sel_i ? dkp_rd_data : ek_rd_data;
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assign dbg_dk_o = dbgdk_in_dkp ? dkp_rd_data :
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dbgdk_in_ek ? ek_rd_data :
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(dbg_dk_idx_i < dk_hek_end) ? hek_r[(dbg_dk_idx_i - dk_ek_end)*8 +: 8]
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: z_i[(dbg_dk_idx_i - dk_hek_end)*8 +: 8];
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// ================================================================
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// Top-level FSM (built incrementally). Stage 2a: G only.
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// ================================================================
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localparam ST_IDLE = 4'd0;
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localparam ST_G = 4'd1; // run G(d||K), capture rho/sigma
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localparam ST_A = 4'd2; // generate A_hat[i][j] via SampleNTT
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localparam ST_C = 4'd3; // generate s[i],e[i] via CBD
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localparam ST_N = 4'd4; // forward NTT of s[i],e[i] in place
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localparam ST_M = 4'd5; // matrix accumulate t_hat = e_hat + sum A o s_hat
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localparam ST_E = 4'd6; // byteEncode12 -> ek/dk BRAM
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localparam ST_H = 4'd7; // H(ek) via multi-block SHA3-256
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localparam ST_DONE = 4'd15;
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reg [3:0] st, st_next;
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reg [255:0] rho_r, sigma_r;
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// A-generation bookkeeping: explicit i/j counters (avoid runtime divide)
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reg [2:0] a_i; // row 0..k-1
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reg [2:0] a_j; // col 0..k-1
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reg [4:0] a_pair; // 0..k*k pairs done (for done test)
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reg [7:0] a_widx; // write index 0..255 within current poly
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reg a_busy; // 1 once current pair's request accepted (gates collect)
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wire [SAW-1:0] a_slot = a_i*k_r + a_j; // A_hat[i][j] slot = i*k + j
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// C-generation bookkeeping: 2*k polys (s[0..k-1] then e[0..k-1])
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reg [4:0] c_poly; // 0..2k
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reg [7:0] c_widx;
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reg c_busy;
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wire [7:0] c_nonce = {3'b0, c_poly}; // s:0..k-1 e:k..2k-1 == nonce
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// slot: c_poly < k -> s_hat[c_poly], else e_hat[c_poly-k]
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wire [SAW-1:0] c_slot = (c_poly < {2'b0, k_r}) ? (slot_s_rt + c_poly)
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: (slot_e_rt + (c_poly - {2'b0, k_r}));
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assign busy_o = (st != ST_IDLE);
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assign done_o = (st == ST_DONE);
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assign dbg_rho_o = rho_r;
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assign dbg_sigma_o = sigma_r;
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// ---- sha3_top in G mode: data_i = {K_byte, d} (d byte0 in [7:0]) ----
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reg sha3_valid;
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wire sha3_ready;
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wire [511:0] sha3_hash;
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wire sha3_vo;
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reg sha3_ack; // consumer ready for hash
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wire [511:0] g_data = {248'b0, 5'b0, k_r, d_i}; // data_i[263:256]=k, [255:0]=d
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// ================================================================
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// Shared keccak_core + phase mux (3 consumers -> 1 core)
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//
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// G/H (u_sha3), SampleNTT (u_snt) and CBD (u_cbd) each need a Keccak
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// permutation, but they run in DISJOINT top-FSM phases (ST_G/ST_H, ST_A,
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// ST_C respectively), so at most one is ever active. One keccak_core
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// serves all three: kc_state_i/kc_valid_i are muxed by phase; kc_valid_o
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// is broadcast but GATED per consumer so an inactive consumer never
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// latches a permutation result meant for another (the samplers latch
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// squeeze state unconditionally on their kc_valid_o input).
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// ================================================================
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wire [1599:0] kc_state_o; // shared core output (to all consumers)
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wire kc_valid_o; // shared core output-valid
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wire kc_ready_o; // shared core input-ready
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// per-consumer drives toward the core
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wire [1599:0] sha3_kc_state_i, snt_kc_state_i, cbd_kc_state_i;
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wire sha3_kc_valid_i, snt_kc_valid_i, cbd_kc_valid_i;
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/* verilator lint_off UNUSEDSIGNAL */
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wire sha3_kc_ready_i, snt_kc_ready_i, cbd_kc_ready_i; // all 1'b1
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/* verilator lint_on UNUSEDSIGNAL */
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|
// phase selects (mutually exclusive)
|
|
wire sel_sha3 = (st == ST_G) || (st == ST_H);
|
|
wire sel_snt = (st == ST_A);
|
|
wire sel_cbd = (st == ST_C);
|
|
|
|
// gated output-valid: only the active consumer sees kc_valid_o
|
|
wire kc_valid_o_sha3 = kc_valid_o & sel_sha3;
|
|
wire kc_valid_o_snt = kc_valid_o & sel_snt;
|
|
wire kc_valid_o_cbd = kc_valid_o & sel_cbd;
|
|
|
|
// input mux: route the active consumer's request to the core
|
|
wire [1599:0] kc_state_i_mux = sel_snt ? snt_kc_state_i :
|
|
sel_cbd ? cbd_kc_state_i :
|
|
sha3_kc_state_i;
|
|
wire kc_valid_i_mux = sel_snt ? snt_kc_valid_i :
|
|
sel_cbd ? cbd_kc_valid_i :
|
|
sel_sha3 ? sha3_kc_valid_i : 1'b0;
|
|
|
|
keccak_core #(.ROUNDS(24)) u_keccak (
|
|
.clk(clk), .rst_n(rst_n),
|
|
.state_i(kc_state_i_mux),
|
|
.valid_i(kc_valid_i_mux),
|
|
.ready_o(kc_ready_o),
|
|
.state_o(kc_state_o),
|
|
.valid_o(kc_valid_o),
|
|
.ready_i(1'b1) // consumers always accept (kc_ready_i=1)
|
|
);
|
|
|
|
// ---- single shared sha3_top serving BOTH G and H ----
|
|
// G (ST_G) uses single-block mode (mb_en=0); H(ek) (ST_H) uses the
|
|
// multi-block absorb path (mb_en=1). These phases are disjoint in the
|
|
// top FSM, so one sha3_top (one keccak_core) is sufficient. mb_en and
|
|
// ready_i are muxed by phase; data_i/mode only matter while mb_en=0.
|
|
wire sha3_mb_en = (st == ST_H);
|
|
sha3_top_shared u_sha3 (
|
|
.clk(clk), .rst_n(rst_n),
|
|
.mode(2'b00), // G = SHA3-512 (only used when mb_en=0)
|
|
.data_i(g_data),
|
|
.valid_i(sha3_valid),
|
|
.ready_o(sha3_ready),
|
|
.hash_o(sha3_hash),
|
|
.valid_o(sha3_vo),
|
|
.ready_i(sha3_mb_en ? h_ack : sha3_ack),
|
|
.mb_en(sha3_mb_en),
|
|
.mb_block_i(h_block_r),
|
|
.mb_valid_i(h_mbvalid),
|
|
.mb_last_i(h_mblast),
|
|
.mb_ready_o(h_mbready),
|
|
// shared keccak_core interface (gated by phase in the mux below)
|
|
.kc_state_o(kc_state_o),
|
|
.kc_valid_o(kc_valid_o_sha3),
|
|
.kc_ready_o(kc_ready_o),
|
|
.kc_state_i(sha3_kc_state_i),
|
|
.kc_valid_i(sha3_kc_valid_i),
|
|
.kc_ready_i(sha3_kc_ready_i)
|
|
);
|
|
|
|
// ---- multi-block H(ek) state (SHA3-256, 6/9/12 blocks); fed to shared u_sha3 ----
|
|
reg [1087:0] h_block_r; // current pre-padded rate block
|
|
reg h_mbvalid;
|
|
reg h_mblast;
|
|
wire h_mbready;
|
|
wire [511:0] h_hash;
|
|
wire h_vo;
|
|
reg h_ack;
|
|
reg [255:0] hek_r; // captured H(ek)
|
|
reg [3:0] h_blk; // 0..H_NBLK-1 block index (up to 11 for K=4)
|
|
reg [7:0] h_byte; // 0..136 byte address being presented (assemble)
|
|
reg [1:0] h_phase; // 0=assemble 1=feed 2=wait-perm 3=done
|
|
// ek BRAM read is registered (1-cycle latency); assemble presents the
|
|
// address for h_byte this cycle and writes the byte that arrived (for the
|
|
// address presented last cycle) into h_block_r. Writeback pipeline regs:
|
|
reg h_wb_vld; // a byte is arriving this cycle
|
|
reg [7:0] h_wb_idx; // its position within the 136-byte block
|
|
reg [11:0] h_wb_g; // its global ek byte index
|
|
reg [7:0] h_wb_pad; // pad constant to use if g is out of ek range
|
|
reg h_wb_inek; // 1 if g is within ek range (use BRAM data)
|
|
|
|
// h_hash / h_vo are now served by the shared u_sha3 above (mb_en=1 during
|
|
// ST_H). They alias the single core's outputs; the H consumer logic below
|
|
// already gates on st==ST_H, and u_sha3's valid_o/hash_o are mb-selected.
|
|
assign h_hash = sha3_hash;
|
|
assign h_vo = sha3_vo;
|
|
|
|
// SHA3-256 over ek (ek_bytes_rt bytes): rate=136. Padded length = h_nblk_rt*136.
|
|
// pad: byte ek_bytes_rt = 0x06 (domain + first pad bit), last byte |= 0x80.
|
|
// byte b (0..135) of block blk: global g = blk*136 + b.
|
|
// ek bytes come from the ek BRAM (registered read); only the pad/zero bytes
|
|
// are constants, returned by h_padconst. Reads runtime ek_bytes_rt/h_last_rt.
|
|
function [7:0] h_padconst(input [3:0] blk, input [7:0] b);
|
|
integer g;
|
|
begin
|
|
g = blk*136 + b;
|
|
if (g == h_last_rt && g == ek_bytes_rt) h_padconst = 8'h86; // 0x06|0x80
|
|
else if (g == ek_bytes_rt) h_padconst = 8'h06;
|
|
else if (g == h_last_rt) h_padconst = 8'h80;
|
|
else h_padconst = 8'h00;
|
|
end
|
|
endfunction
|
|
|
|
// Global ek byte index for the address currently presented in ST_H assemble.
|
|
wire [11:0] h_g_addr = {8'd0, h_blk} * 12'd136 + {4'd0, h_byte};
|
|
|
|
// ek BRAM read-address mux: ST_H assemble drives it; otherwise debug readback.
|
|
// dbg_dk ek-region takes priority (its loop runs after the ek loop), so the
|
|
// single read port serves dbg_byte_o (ek loop) then dbg_dk_o (dk loop).
|
|
wire [11:0] dbgdk_ek_off = dbg_dk_idx_i - dk_bytes_rt; // offset within ek region
|
|
assign ek_rd_addr = (st == ST_H) ? h_g_addr[10:0] :
|
|
dbgdk_in_ek ? dbgdk_ek_off[10:0]
|
|
: dbg_byte_idx_i;
|
|
// dkp BRAM read-address mux: dbg_byte (sel=1) or dbg_dk (dkp region).
|
|
assign dkp_rd_addr = dbg_byte_sel_i ? dbg_byte_idx_i : dbg_dk_idx_i[10:0];
|
|
|
|
// ---- sample_ntt_sync: Â[i][j] = SampleNTT(rho || j || i) ----
|
|
reg snt_valid;
|
|
wire snt_ready;
|
|
wire [11:0] snt_coeff;
|
|
wire snt_vo;
|
|
wire snt_last;
|
|
reg snt_ack; // we accept coeffs
|
|
|
|
sample_ntt_sync_shared #(.K(KMAX)) u_snt (
|
|
.clk(clk), .rst_n(rst_n),
|
|
.rho_i(rho_r),
|
|
.k_i(k_r),
|
|
.i_idx(a_i[1:0]),
|
|
.j_idx(a_j[1:0]),
|
|
.valid_i(snt_valid),
|
|
.ready_o(snt_ready),
|
|
.coeff_o(snt_coeff),
|
|
.valid_o(snt_vo),
|
|
.ready_i(snt_ack),
|
|
.last_o(snt_last),
|
|
// shared keccak_core interface
|
|
.kc_state_o(kc_state_o),
|
|
.kc_valid_o(kc_valid_o_snt),
|
|
.kc_ready_o(kc_ready_o),
|
|
.kc_state_i(snt_kc_state_i),
|
|
.kc_valid_i(snt_kc_valid_i),
|
|
.kc_ready_i(snt_kc_ready_i)
|
|
);
|
|
|
|
// ---- sample_cbd_sync: s[i]=CBD3(PRF(sigma,i)), e[i]=CBD3(PRF(sigma,K+i)) ----
|
|
reg cbd_valid;
|
|
wire cbd_ready;
|
|
wire [11:0] cbd_coeff; // 12-bit signed (two's complement)
|
|
wire cbd_vo;
|
|
wire cbd_last;
|
|
reg cbd_ack;
|
|
|
|
sample_cbd_sync_shared u_cbd (
|
|
.clk(clk), .rst_n(rst_n),
|
|
.seed_i(sigma_r),
|
|
.nonce_i(c_nonce),
|
|
.eta_i(eta1_rt),
|
|
.valid_i(cbd_valid),
|
|
.ready_o(cbd_ready),
|
|
.coeff_o(cbd_coeff),
|
|
.valid_o(cbd_vo),
|
|
.ready_i(cbd_ack),
|
|
.last_o(cbd_last),
|
|
// shared keccak_core interface
|
|
.kc_state_o(kc_state_o),
|
|
.kc_valid_o(kc_valid_o_cbd),
|
|
.kc_ready_o(kc_ready_o),
|
|
.kc_state_i(cbd_kc_state_i),
|
|
.kc_valid_i(cbd_kc_valid_i),
|
|
.kc_ready_i(cbd_kc_ready_i)
|
|
);
|
|
|
|
// signed (two's complement) -> [0,Q): add Q when negative
|
|
wire [11:0] cbd_modq = cbd_coeff[11] ? (cbd_coeff + 12'(Q)) : cbd_coeff;
|
|
|
|
// ---- ntt_core: forward NTT (mode=0, no scaling) of s[i],e[i] in place ----
|
|
// N-stage bookkeeping: process slots S0,S1,E0,E1 (= SLOT_S0 + n_slot).
|
|
reg [4:0] n_slot; // 0..2K (process s_hat[0..K-1] then e_hat[0..K-1])
|
|
reg [8:0] n_ridx; // load read-AHEAD pointer 0..256 (leads consume by 1)
|
|
reg [7:0] n_widx; // output write index 0..255
|
|
reg n_valid; // feeding coeffs to ntt_core (delayed 1 cyc vs n_ridx)
|
|
reg n_loading; // 1 while presenting load addresses to bank_se
|
|
reg n_pending; // waiting for ntt_core IDLE to start next slot
|
|
wire [SAW-1:0] n_slot_addr = slot_s_rt + n_slot; // s_hat then e_hat contiguous
|
|
|
|
wire ntt_ready;
|
|
wire [11:0] ntt_coeff;
|
|
wire ntt_vo;
|
|
wire ntt_done;
|
|
// bank_se read addr for the NTT load (relative slot = n_slot); sd_bram
|
|
// registers it into bse_rd_data, which feeds ntt_core 1 cycle later.
|
|
wire [13:0] ntt_rd_full = n_slot*256 + n_ridx[7:0];
|
|
wire [11:0] ntt_in = bse_rd_data;
|
|
|
|
ntt_core u_ntt (
|
|
.clk(clk), .rst_n(rst_n),
|
|
.coeff_in(ntt_in),
|
|
.valid_i(n_valid),
|
|
.ready_o(ntt_ready),
|
|
.mode(1'b0), // forward NTT, no scaling
|
|
.coeff_out(ntt_coeff),
|
|
.valid_o(ntt_vo),
|
|
.ready_i(1'b1), // always accept output
|
|
.done_o(ntt_done)
|
|
);
|
|
|
|
// ---- poly_mul_sync: t_hat[i] = e_hat[i] + sum_j A_hat[i][j] o s_hat[j] ----
|
|
// M-stage bookkeeping. For each (i,j): LOAD 256 (A,shat) pairs, then accumulate
|
|
// 256 products into T_i (init from E_i when j==0, else from running T_i).
|
|
reg [2:0] m_i; // row 0..K (needs to reach K to exit)
|
|
reg [2:0] m_j; // col 0..K-1
|
|
reg [8:0] m_ld; // load index 0..256
|
|
reg [7:0] m_oidx; // output/accum index 0..255
|
|
reg m_loading; // 1 while streaming pairs into poly_mul
|
|
reg m_pending; // wait for poly_mul IDLE before next (i,j)
|
|
|
|
// ---- Stage 2f: byteEncode12 serializer ----
|
|
// Pack each poly (2 coeffs -> 3 bytes, LSB-first 12-bit). ek = t_hat[0..K-1]
|
|
// bytes || rho; dk_pke = s_hat[0..K-1] bytes. Walk coeff pairs per poly.
|
|
reg [4:0] e_poly; // 0..2K-1: [0,K) = t_hat -> ek; [K,2K) = s_hat -> dk_pke
|
|
reg [7:0] e_pair; // 0..127 coeff-pair within poly
|
|
reg [9:0] e_rho; // 0..31 rho byte copy index (ek tail)
|
|
reg e_done; // serialization complete
|
|
// source poly slot: t_hat[e_poly] for ek half, s_hat[e_poly-K] for dk half
|
|
wire e_is_dk = (e_poly >= {1'b0, k_r});
|
|
wire [4:0] e_pidx = e_is_dk ? (e_poly - {1'b0, k_r}) : e_poly; // index within target
|
|
// Registered single-port read (sd_bram timing). One bank read per cycle:
|
|
// ek half reads bank_t (t_hat), dk half reads bank_se (s_hat). The two
|
|
// coeffs of a pair are serialized across a 4-cycle micro-phase e_ph:
|
|
// 0 = fetch c0
|
|
// 1 = c0 ready: write b0, save c0[11:8], fetch c1
|
|
// 2 = c1 ready: write b1, save c1[11:4]
|
|
// 3 = write b2, advance pair
|
|
reg [1:0] e_ph; // per-pair micro-phase 0..3
|
|
reg [3:0] e_c0_hi; // saved c0[11:8] for b1
|
|
reg [7:0] e_c1_hi; // saved c1[11:4] for b2
|
|
wire e_rd_half = (e_ph == 2'd1); // ph0 -> c0, ph1 -> c1
|
|
wire [13:0] e_rd_full = e_pidx*256 + {e_pair, e_rd_half}; // bse/bt rd addr in ST_E
|
|
// dk half reads bank_se (bse_rd_data), ek half reads bank_t (bt_rd_data);
|
|
// both registered inside their sd_bram with the same 1-cycle latency, so
|
|
// the coeff for the addr presented last cycle is selected here.
|
|
wire [11:0] e_rd_coeff = e_is_dk ? bse_rd_data : bt_rd_data;
|
|
// byteEncode write byte offset within the target memory: pair*3 + byte index.
|
|
wire [11:0] e_base = e_pidx * 12'd384; // poly index *384 (=128 pairs*3)
|
|
wire [11:0] e_boff = e_base + {e_pair, 1'b0} + {2'b0, e_pair}; // pair*3
|
|
wire [1:0] e_wb = e_ph - 2'd1; // ph1->byte0, ph2->byte1, ph3->byte2
|
|
wire [7:0] e_wbyte = (e_ph == 2'd1) ? e_rd_coeff[7:0] // b0 = c0[7:0]
|
|
: (e_ph == 2'd2) ? {e_rd_coeff[3:0], e_c0_hi} // b1 = {c1[3:0],c0[11:8]}
|
|
: e_c1_hi; // b2 = c1[11:4]
|
|
|
|
wire [SAW-1:0] m_aslot = m_i*k_r + m_j; // A_hat[i][j] slot = i*k + j
|
|
wire [SAW-1:0] m_sslot = slot_s_rt + m_j; // s_hat[j]
|
|
wire [SAW-1:0] m_eslot = slot_e_rt + m_i; // e_hat[i]
|
|
wire [SAW-1:0] m_tslot = slot_t_rt + m_i; // t_hat[i]
|
|
|
|
reg pm_valid;
|
|
wire pm_ready;
|
|
wire [11:0] pm_coeff;
|
|
wire pm_vo;
|
|
// pm_a: A_hat[i][j] in bank_a (abs slot m_aslot). pm_b: s_hat[j] in
|
|
// bank_se (relative slot = m_sslot - slot_s_rt = m_j). m_ld is a read-ahead
|
|
// pointer; both bank reads come from their sd_bram (registered, 1-cycle
|
|
// latency) and feed poly_mul one cycle later (pm_valid delayed 1 cyc).
|
|
wire [13:0] pm_a_full = m_aslot*256 + m_ld[7:0];
|
|
wire [13:0] pm_b_full = m_j*256 + m_ld[7:0];
|
|
wire [11:0] pm_a_in = ba_rd_data; // bank_a sd_bram registered read
|
|
wire [11:0] pm_b_in = bse_rd_data; // bank_se sd_bram registered read (load phase)
|
|
|
|
poly_mul_sync u_pmul (
|
|
.clk(clk), .rst_n(rst_n),
|
|
.coeff_a_in(pm_a_in),
|
|
.coeff_b_in(pm_b_in),
|
|
.valid_i(pm_valid),
|
|
.ready_o(pm_ready),
|
|
.coeff_out(pm_coeff),
|
|
.valid_o(pm_vo),
|
|
.ready_i(1'b1)
|
|
);
|
|
|
|
// accumulator source: e_hat[i] for first term (j==0), else running t_hat[i].
|
|
// e_hat[i] lives in bank_se at relative slot (slot_e_rt-slot_s_rt + m_i) = K+m_i.
|
|
// t_hat[i] lives in bank_t at relative slot m_i. Both reads come from their
|
|
// sd_bram (bse_rd_data / bt_rd_data) with the same 1-cycle latency.
|
|
// Registered read-ahead: present the index the NEXT pm_vo will consume
|
|
// m_acc_radr = pm_vo ? m_oidx+1 : m_oidx
|
|
// The j-select is applied on the registered outputs (m_jq = (m_j==0)
|
|
// delayed 1 cyc to align with the read latency). RMW read-old holds: read
|
|
// addr (m_oidx+1) leads write addr (m_oidx). Cadence CALC/C0/C1.
|
|
wire [7:0] m_acc_radr = pm_vo ? (m_oidx + 8'd1) : m_oidx;
|
|
wire [13:0] m_eacc_full = ({2'b0, k_r} + {2'b0, m_i})*256 + m_acc_radr; // K+m_i (bse_rd_addr in acc)
|
|
wire [13:0] m_tacc_full = m_i*256 + m_acc_radr; // bt_rd_addr
|
|
reg m_jq; // (m_j==0) delayed 1 cyc to match read latency
|
|
// selected accumulator source aligned with pm_coeff
|
|
wire [11:0] m_acc_src = m_jq ? bse_rd_data : bt_rd_data;
|
|
// (a + b) mod Q (both < Q, sum < 2Q): one conditional subtract
|
|
wire [12:0] m_sum = {1'b0, m_acc_src} + {1'b0, pm_coeff};
|
|
wire [11:0] m_accq = (m_sum >= 13'(Q)) ? (m_sum - 13'(Q)) : m_sum[11:0];
|
|
|
|
always @(*) begin
|
|
st_next = st;
|
|
case (st)
|
|
ST_IDLE: if (start_i) st_next = ST_G;
|
|
ST_G: if (sha3_vo) st_next = ST_A;
|
|
ST_A: if (a_pair >= kk_rt) st_next = ST_C;
|
|
ST_C: if (c_poly >= {1'b0, k_r, 1'b0}) st_next = ST_N;
|
|
ST_N: if (n_slot >= {1'b0, k_r, 1'b0}) st_next = ST_M;
|
|
ST_M: if (m_i >= k_r) st_next = ST_E;
|
|
ST_E: if (e_done) st_next = ST_H;
|
|
ST_H: if (h_phase == 2'd3) st_next = ST_DONE;
|
|
ST_DONE: st_next = ST_IDLE;
|
|
default: st_next = ST_IDLE;
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk or negedge rst_n) begin
|
|
if (!rst_n) begin
|
|
st <= ST_IDLE;
|
|
k_r <= 3'd0;
|
|
rho_r <= 256'd0;
|
|
sigma_r <= 256'd0;
|
|
sha3_valid <= 1'b0;
|
|
sha3_ack <= 1'b0;
|
|
snt_valid <= 1'b0;
|
|
snt_ack <= 1'b0;
|
|
a_pair <= 5'd0;
|
|
a_i <= 3'd0;
|
|
a_j <= 3'd0;
|
|
a_widx <= 8'd0;
|
|
a_busy <= 1'b0;
|
|
cbd_valid <= 1'b0;
|
|
cbd_ack <= 1'b0;
|
|
c_poly <= 3'd0;
|
|
c_widx <= 8'd0;
|
|
c_busy <= 1'b0;
|
|
n_slot <= 3'd0;
|
|
n_ridx <= 9'd0;
|
|
n_widx <= 8'd0;
|
|
n_valid <= 1'b0;
|
|
n_loading <= 1'b0;
|
|
n_pending <= 1'b0;
|
|
m_i <= 2'd0;
|
|
m_j <= 2'd0;
|
|
m_ld <= 9'd0;
|
|
m_oidx <= 8'd0;
|
|
m_loading <= 1'b0;
|
|
m_pending <= 1'b0;
|
|
pm_valid <= 1'b0;
|
|
m_jq <= 1'b0;
|
|
e_poly <= 3'd0;
|
|
e_pair <= 8'd0;
|
|
e_ph <= 2'd0;
|
|
e_c0_hi <= 4'd0;
|
|
e_c1_hi <= 8'd0;
|
|
e_rho <= 10'd0;
|
|
e_done <= 1'b0;
|
|
ek_we <= 1'b0;
|
|
dkp_we <= 1'b0;
|
|
ek_wa <= 11'd0;
|
|
dkp_wa <= 11'd0;
|
|
ek_wd <= 8'd0;
|
|
dkp_wd <= 8'd0;
|
|
h_block_r <= 1088'd0;
|
|
h_mbvalid <= 1'b0;
|
|
h_mblast <= 1'b0;
|
|
h_ack <= 1'b0;
|
|
hek_r <= 256'd0;
|
|
h_blk <= 3'd0;
|
|
h_byte <= 8'd0;
|
|
h_phase <= 2'd0;
|
|
h_wb_vld <= 1'b0;
|
|
h_wb_idx <= 8'd0;
|
|
h_wb_g <= 12'd0;
|
|
h_wb_pad <= 8'd0;
|
|
h_wb_inek <= 1'b0;
|
|
end else begin
|
|
st <= st_next;
|
|
|
|
// BRAM write-enables default low; pulsed where a byte is written.
|
|
ek_we <= 1'b0;
|
|
dkp_we <= 1'b0;
|
|
|
|
// Kick off G when entering ST_G
|
|
if (st == ST_IDLE && start_i) begin
|
|
k_r <= k_i; // capture runtime ML-KEM param
|
|
sha3_valid <= 1'b1;
|
|
sha3_ack <= 1'b1;
|
|
end
|
|
// Drop valid once accepted
|
|
if (sha3_valid && sha3_ready) sha3_valid <= 1'b0;
|
|
|
|
// Capture rho/sigma when G completes; arm A stage
|
|
if (st == ST_G && sha3_vo) begin
|
|
rho_r <= sha3_hash[255:0]; // rho = G output bytes 0..31
|
|
sigma_r <= sha3_hash[511:256]; // sigma = bytes 32..63
|
|
sha3_ack <= 1'b0;
|
|
snt_valid <= 1'b1; // start first SampleNTT
|
|
snt_ack <= 1'b1;
|
|
a_pair <= 5'd0;
|
|
a_i <= 3'd0;
|
|
a_j <= 3'd0;
|
|
a_widx <= 8'd0;
|
|
a_busy <= 1'b0;
|
|
end
|
|
|
|
// ---- ST_A: drive SampleNTT, store 256 coeffs per pair ----
|
|
if (st == ST_A) begin
|
|
// mark busy once this pair's request accepted
|
|
if (snt_valid && snt_ready) begin
|
|
snt_valid <= 1'b0;
|
|
a_busy <= 1'b1;
|
|
end
|
|
|
|
// store each output coefficient only while busy (ignore stale
|
|
// last coeff from prior poly). The bank_a write itself is the
|
|
// combinational ba_we/ba_wa/ba_wd assigns above; here we only
|
|
// advance the write index and (i,j) bookkeeping.
|
|
if (a_busy && snt_vo && snt_ack) begin
|
|
if (snt_last) begin
|
|
// finished this poly; advance (i,j) in row-major order
|
|
a_pair <= a_pair + 5'd1;
|
|
a_widx <= 8'd0;
|
|
a_busy <= 1'b0;
|
|
if (a_j + 3'd1 < k_r) begin
|
|
a_j <= a_j + 3'd1;
|
|
end else begin
|
|
a_j <= 3'd0;
|
|
a_i <= a_i + 3'd1;
|
|
end
|
|
// start next SampleNTT if more pairs remain
|
|
if (a_pair + 5'd1 < kk_rt) snt_valid <= 1'b1;
|
|
end else begin
|
|
a_widx <= a_widx + 8'd1;
|
|
end
|
|
end
|
|
end
|
|
|
|
// Arm C stage when A finishes
|
|
if (st == ST_A && st_next == ST_C) begin
|
|
cbd_valid <= 1'b1;
|
|
cbd_ack <= 1'b1;
|
|
c_poly <= 3'd0;
|
|
c_widx <= 8'd0;
|
|
c_busy <= 1'b0;
|
|
end
|
|
|
|
// ---- ST_C: drive CBD, store 256 mod-q coeffs per poly ----
|
|
if (st == ST_C) begin
|
|
if (cbd_valid && cbd_ready) begin
|
|
cbd_valid <= 1'b0;
|
|
c_busy <= 1'b1;
|
|
end
|
|
|
|
if (c_busy && cbd_vo && cbd_ack) begin
|
|
// bank_se write is the combinational bse_we/bse_wa/bse_wd
|
|
// assigns (rel slot c_poly); here only advance counters.
|
|
if (cbd_last) begin
|
|
c_poly <= c_poly + 3'd1;
|
|
c_widx <= 8'd0;
|
|
c_busy <= 1'b0;
|
|
if (c_poly + 3'd1 < {1'b0, k_r, 1'b0}) cbd_valid <= 1'b1;
|
|
end else begin
|
|
c_widx <= c_widx + 8'd1;
|
|
end
|
|
end
|
|
end
|
|
|
|
// Arm N stage when C finishes: prime load of slot S0. n_ridx is a
|
|
// read-ahead pointer; bank_se read is registered inside sd_bram (bse_rd_data)
|
|
// and fed to ntt_core one cycle later, so valid starts low (priming).
|
|
if (st == ST_C && st_next == ST_N) begin
|
|
n_slot <= 3'd0;
|
|
n_ridx <= 9'd0;
|
|
n_widx <= 8'd0;
|
|
n_valid <= 1'b0;
|
|
n_loading <= 1'b1; // begin presenting load addresses
|
|
n_pending <= 1'b0;
|
|
end
|
|
|
|
// ---- ST_N: forward NTT each of S0,S1,E0,E1 in place ----
|
|
if (st == ST_N) begin
|
|
// LOAD phase: present read-ahead addr to bank_se (bse_rd_addr);
|
|
// sd_bram registers it, so bse_rd_data is consumed by ntt_core
|
|
// one cycle later (n_valid). Cores hold ready high through LOAD,
|
|
// so a fixed 1-cycle skew suffices (no backpressure gating).
|
|
if (n_loading) begin
|
|
if (n_ridx == 9'd256) begin
|
|
// 256th coeff consumed this cycle; stop presenting addr
|
|
n_loading <= 1'b0;
|
|
n_valid <= 1'b0;
|
|
end else begin
|
|
n_ridx <= n_ridx + 9'd1;
|
|
n_valid <= 1'b1; // data presented last cycle is valid
|
|
end
|
|
end
|
|
|
|
// OUTPUT phase: collect 256 results, write back to same slot.
|
|
// The bank_se write is the combinational bse_we/bse_wa/bse_wd
|
|
// assigns (rel slot n_slot); here only advance the write index.
|
|
if (ntt_vo) begin
|
|
n_widx <= n_widx + 8'd1; // wraps 255->0 after last
|
|
end
|
|
|
|
// Slot complete when ntt_core returns to DONE
|
|
if (ntt_done) begin
|
|
if (n_slot + 3'd1 < {1'b0, k_r, 1'b0}) begin
|
|
n_slot <= n_slot + 3'd1;
|
|
n_widx <= 8'd0;
|
|
n_pending <= 1'b1; // wait one cycle for core IDLE
|
|
end else begin
|
|
n_slot <= n_slot + 3'd1; // == 2K -> ST_DONE
|
|
end
|
|
end
|
|
|
|
// Kick next slot's load once core is back IDLE (re-prime)
|
|
if (n_pending && ntt_ready && !ntt_done) begin
|
|
n_ridx <= 9'd0;
|
|
n_valid <= 1'b0;
|
|
n_loading <= 1'b1;
|
|
n_pending <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// Arm M stage when N finishes: prime first (i=0,j=0) poly_mul load.
|
|
// m_ld read-ahead pointer; bank_a/bank_se sd_bram reads land 1 cyc
|
|
// later, pm_valid asserted one cycle after an address is presented.
|
|
if (st == ST_N && st_next == ST_M) begin
|
|
m_i <= 2'd0;
|
|
m_j <= 2'd0;
|
|
m_ld <= 9'd0;
|
|
m_oidx <= 8'd0;
|
|
m_loading <= 1'b1;
|
|
m_pending <= 1'b0;
|
|
pm_valid <= 1'b0;
|
|
end
|
|
|
|
// ---- ST_M: t_hat[i] = e_hat[i] + sum_j A[i][j] o s_hat[j] ----
|
|
if (st == ST_M) begin
|
|
// accumulator reads come from sd_bram (bse_rd_data e_hat /
|
|
// bt_rd_data t_hat). m_jq aligns the j-select with the 1-cycle
|
|
// read latency. (bse_rd_addr muxes load vs acc by m_loading.)
|
|
m_jq <= (m_j == 2'd0);
|
|
|
|
// LOAD: present read-ahead addr to bank_a/bank_se via their
|
|
// sd_bram read ports (ba_rd_addr=pm_a_full, bse_rd_addr=pm_b_full
|
|
// while m_loading); ba_rd_data/bse_rd_data land next cycle and
|
|
// are consumed by poly_mul (pm_valid). poly_mul holds ready high
|
|
// through LOAD, so a fixed 1-cycle skew suffices.
|
|
if (m_loading) begin
|
|
if (m_ld == 9'd256) begin
|
|
pm_valid <= 1'b0; // 256th pair consumed this cycle
|
|
m_loading <= 1'b0;
|
|
m_ld <= 9'd0;
|
|
m_oidx <= 8'd0;
|
|
end else begin
|
|
m_ld <= m_ld + 9'd1;
|
|
pm_valid <= 1'b1; // pair presented last cycle is valid
|
|
end
|
|
end
|
|
|
|
// ACCUMULATE: each product coeff += e_hat (j==0) or running t_hat.
|
|
// The bank_t write is the combinational bt_we/bt_wa/bt_wd assigns
|
|
// below; here we only advance the accumulate index / (i,j).
|
|
if (pm_vo) begin
|
|
if (m_oidx == 8'd255) begin
|
|
// finished this (i,j) term; advance
|
|
if (m_j + 2'd1 < k_r) begin
|
|
m_j <= m_j + 2'd1;
|
|
m_pending <= 1'b1; // next term, same row
|
|
end else begin
|
|
m_j <= 2'd0;
|
|
m_i <= m_i + 2'd1; // next row (or == K -> DONE)
|
|
if (m_i + 2'd1 < k_r) m_pending <= 1'b1;
|
|
end
|
|
end else begin
|
|
m_oidx <= m_oidx + 8'd1;
|
|
end
|
|
end
|
|
|
|
// Start next (i,j) poly_mul load once core is IDLE again (re-prime)
|
|
if (m_pending && pm_ready && !pm_vo) begin
|
|
m_loading <= 1'b1;
|
|
m_ld <= 9'd0;
|
|
m_oidx <= 8'd0;
|
|
pm_valid <= 1'b0;
|
|
m_pending <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// Arm E stage when M finishes
|
|
if (st == ST_M && st_next == ST_E) begin
|
|
e_poly <= 3'd0;
|
|
e_pair <= 8'd0;
|
|
e_ph <= 2'd0; // start at fetch-c0 of first pair
|
|
e_rho <= 10'd0;
|
|
e_done <= 1'b0;
|
|
end
|
|
|
|
// ---- ST_E: byteEncode12 t_hat -> ek, s_hat -> dk_pke ----
|
|
// Single registered bank read per cycle; 4-cycle micro-phase per
|
|
// coeff pair (ph0 fetch c0, ph1 write b0 + fetch c1, ph2 write b1,
|
|
// ph3 write b2). The coeff for the addr presented last cycle is
|
|
// e_rd_coeff (= bse_rd_data for dk-half, bt_rd_data for ek-half),
|
|
// both registered inside their sd_bram (bse_rd_addr/bt_rd_addr =
|
|
// e_rd_full in ST_E).
|
|
if (st == ST_E && !e_done) begin
|
|
if (e_poly < {1'b0, k_r, 1'b0}) begin
|
|
// ph0: fetch only (prime). ph1..3: write one packed byte.
|
|
if (e_ph != 2'd0) begin
|
|
if (!e_is_dk) begin
|
|
ek_we <= 1'b1;
|
|
ek_wa <= e_boff[10:0] + {9'd0, e_wb};
|
|
ek_wd <= e_wbyte;
|
|
end else begin
|
|
dkp_we <= 1'b1;
|
|
dkp_wa <= e_boff[10:0] + {9'd0, e_wb};
|
|
dkp_wd <= e_wbyte;
|
|
end
|
|
end
|
|
// save coeff high nibbles as they become available
|
|
if (e_ph == 2'd1) e_c0_hi <= e_rd_coeff[11:8]; // c0[11:8]
|
|
if (e_ph == 2'd2) e_c1_hi <= e_rd_coeff[11:4]; // c1[11:4]
|
|
|
|
// advance micro-phase / pair / poly
|
|
if (e_ph == 2'd3) begin
|
|
e_ph <= 2'd0;
|
|
if (e_pair == 8'd127) begin
|
|
e_pair <= 8'd0;
|
|
e_poly <= e_poly + 5'd1; // next poly or -> rho phase
|
|
end else begin
|
|
e_pair <= e_pair + 8'd1;
|
|
end
|
|
end else begin
|
|
e_ph <= e_ph + 2'd1;
|
|
end
|
|
end else begin
|
|
// rho copy: ek[384*K + r] = rho byte r (r = 0..31), 1 byte/cycle
|
|
ek_we <= 1'b1;
|
|
ek_wa <= dk_bytes_rt[10:0] + {1'b0, e_rho};
|
|
ek_wd <= rho_r[e_rho*8 +: 8];
|
|
if (e_rho == 10'd31) e_done <= 1'b1;
|
|
else e_rho <= e_rho + 10'd1;
|
|
end
|
|
end
|
|
|
|
// Arm H stage when E finishes
|
|
if (st == ST_E && st_next == ST_H) begin
|
|
h_blk <= 3'd0;
|
|
h_byte <= 8'd0;
|
|
h_phase <= 2'd0; // assemble
|
|
h_mbvalid<= 1'b0;
|
|
h_mblast <= 1'b0;
|
|
h_ack <= 1'b1; // ready to consume final digest
|
|
h_wb_vld <= 1'b0; // no pending writeback yet
|
|
end
|
|
|
|
// ---- ST_H: H(ek) via multi-block SHA3-256 (6/9/12 pre-padded blocks) ----
|
|
if (st == ST_H) begin
|
|
case (h_phase)
|
|
// assemble 136 bytes of block h_blk into h_block_r.
|
|
// ek BRAM read is registered: present addr for h_byte this
|
|
// cycle, write back the byte that arrived for the addr we
|
|
// presented last cycle (h_wb_*). h_byte runs 0..136 (one
|
|
// extra cycle to flush the final writeback).
|
|
2'd0: begin
|
|
// writeback the byte read for the previous address
|
|
if (h_wb_vld)
|
|
h_block_r[h_wb_idx*8 +: 8] <= h_wb_inek ? ek_rd_data : h_wb_pad;
|
|
|
|
if (h_byte <= 8'd135) begin
|
|
// set up writeback for the address presented this cycle
|
|
h_wb_vld <= 1'b1;
|
|
h_wb_idx <= h_byte;
|
|
h_wb_g <= h_g_addr;
|
|
h_wb_inek <= (h_g_addr < ek_bytes_rt);
|
|
h_wb_pad <= h_padconst(h_blk, h_byte);
|
|
h_byte <= h_byte + 8'd1;
|
|
end else begin
|
|
// h_byte==136: final writeback (for byte 135) done above
|
|
h_wb_vld <= 1'b0;
|
|
h_byte <= 8'd0;
|
|
h_mbvalid <= 1'b1;
|
|
h_mblast <= (h_blk == h_nblk_rt - 4'd1);
|
|
h_phase <= 2'd1; // feed
|
|
end
|
|
end
|
|
// feed: hold valid until accepted (mb_ready drops)
|
|
2'd1: begin
|
|
if (h_mbvalid && !h_mbready) begin
|
|
h_mbvalid <= 1'b0;
|
|
h_mblast <= 1'b0;
|
|
h_phase <= 2'd2; // wait permute
|
|
end
|
|
end
|
|
// wait permute done: ready again (more blocks) or digest valid (last)
|
|
2'd2: begin
|
|
if (h_vo) begin
|
|
hek_r <= h_hash[255:0];
|
|
h_phase <= 2'd3; // done
|
|
end else if (h_mbready) begin
|
|
h_blk <= h_blk + 3'd1;
|
|
h_phase <= 2'd0; // assemble next block
|
|
end
|
|
end
|
|
default: ; // 2'd3 done: hold
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|