193 lines
7.5 KiB
Plaintext
193 lines
7.5 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Tue Jul 7 15:28:57 2026
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| Host : fedora running 64-bit unknown
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| Command : report_utilization -file /home/fallensigh/Dev/mlkem/reports/util_synth.rpt
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| Design : mlkem_top
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| Device : 7a200tfbg676-1
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| Design State : Synthesized
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+----------------------------+-------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+-------+-------+-----------+-------+
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| Slice LUTs* | 32814 | 0 | 134600 | 24.38 |
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| LUT as Logic | 32777 | 0 | 134600 | 24.35 |
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| LUT as Memory | 37 | 0 | 46200 | 0.08 |
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| LUT as Distributed RAM | 0 | 0 | | |
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| LUT as Shift Register | 37 | 0 | | |
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| Slice Registers | 23737 | 0 | 269200 | 8.82 |
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| Register as Flip Flop | 23737 | 0 | 269200 | 8.82 |
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| Register as Latch | 0 | 0 | 269200 | 0.00 |
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| F7 Muxes | 3384 | 0 | 67300 | 5.03 |
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| F8 Muxes | 1205 | 0 | 33650 | 3.58 |
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+----------------------------+-------+-------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 3 | Yes | - | Set |
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| 23614 | Yes | - | Reset |
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| 0 | Yes | Set | - |
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| 120 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+-------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------+------+-------+-----------+-------+
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| Block RAM Tile | 5 | 0 | 365 | 1.37 |
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| RAMB36/FIFO* | 2 | 0 | 365 | 0.55 |
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| RAMB36E1 only | 2 | | | |
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| RAMB18 | 6 | 0 | 730 | 0.82 |
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| RAMB18E1 only | 6 | | | |
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+-------------------+------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+-----------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------+------+-------+-----------+-------+
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| DSPs | 0 | 0 | 740 | 0.00 |
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+-----------+------+-------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+-----------+--------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------------------------+------+-------+-----------+--------+
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| Bonded IOB | 3228 | 0 | 400 | 807.00 |
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| Bonded IPADs | 0 | 0 | 26 | 0.00 |
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| Bonded OPADs | 0 | 0 | 16 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
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| PHASER_REF | 0 | 0 | 10 | 0.00 |
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| OUT_FIFO | 0 | 0 | 40 | 0.00 |
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| IN_FIFO | 0 | 0 | 40 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
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| IBUFDS | 0 | 0 | 384 | 0.00 |
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| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
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| ILOGIC | 0 | 0 | 400 | 0.00 |
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| OLOGIC | 0 | 0 | 400 | 0.00 |
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+-----------------------------+------+-------+-----------+--------+
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5. Clocking
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-----------
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+------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+------------+------+-------+-----------+-------+
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| BUFGCTRL | 1 | 0 | 32 | 3.13 |
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| BUFIO | 0 | 0 | 40 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
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| BUFMRCE | 0 | 0 | 20 | 0.00 |
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| BUFHCE | 0 | 0 | 120 | 0.00 |
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| BUFR | 0 | 0 | 40 | 0.00 |
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+------------+------+-------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------+------+-------+-----------+-------+
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| BSCANE2 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+-----------+-------+
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7. Primitives
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-------------
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+----------+-------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+-------+---------------------+
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| FDCE | 23614 | Flop & Latch |
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| LUT6 | 17906 | LUT |
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| LUT3 | 8519 | LUT |
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| LUT5 | 5910 | LUT |
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| MUXF7 | 3384 | MuxFx |
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| LUT4 | 3044 | LUT |
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| LUT2 | 2820 | LUT |
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| OBUF | 2342 | IO |
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| MUXF8 | 1205 | MuxFx |
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| IBUF | 886 | IO |
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| CARRY4 | 879 | CarryLogic |
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| LUT1 | 208 | LUT |
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| FDRE | 120 | Flop & Latch |
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| SRL16E | 37 | Distributed Memory |
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| RAMB18E1 | 6 | Block Memory |
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| FDPE | 3 | Flop & Latch |
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| RAMB36E1 | 2 | Block Memory |
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| BUFG | 1 | Clock |
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+----------+-------+---------------------+
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8. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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