FallenSigh
8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
63 lines
1.8 KiB
Markdown
63 lines
1.8 KiB
Markdown
# Verilator RTL Conventions
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## Verilator Version
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**5.046** (Fedora package). Requires **C++14** or later.
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## Compile Arguments
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**Do NOT** add `-CFLAGS -std=c++11`. Verilator 5.046 uses C++14 features (`""s` string literal).
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Let Verilator use its default C++ standard.
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Correct base command:
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```
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verilator -Wall --cc --build --timing --exe --top-module <top> <rtl> <tb.cpp>
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```
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## Include Paths
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All Verilog files use paths relative to project root (`~/Dev/mlkem`).
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Pass `+incdir+<project_root>` to Verilator so `\`include "sync_rtl/common/defines.vh"` resolves.
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## Clock Period
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100MHz = 10ns. Defined centrally in `sync_rtl/common/defines.vh`:
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```verilog
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`define CLK_PERIOD 10.0
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```
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## Testbench Timing Protocol (Verilator C++)
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### Critical Rule: Always advance at least one posedge before checking signals
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Setting a DUT input (e.g., `dut->valid_i = 1`) does NOT take effect until `dut->eval()` is called.
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A posedge requires: `dut->clk = 1; dut->eval();`.
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### pipeline_reg valid/ready timing
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The `pipeline_reg` module's valid_o is HIGH for exactly ONE cycle between the posedge that captures data and the next posedge that consumes it (when ready_i=1).
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Correct read pattern:
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```cpp
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// 1. Drive input + posedge → data captured, valid_o → 1
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dut->valid_i = 1;
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posedge(dut); // dut->clk = 1; eval(); dut->clk = 0; eval();
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dut->valid_i = 0;
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// 2. Read result NOW (valid_o is high, sum is valid)
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printf("RESULT: %03X\n", dut->sum & 0xFFF);
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// 3. Consume with next posedge → valid_o → 0
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posedge(dut);
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```
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### Anti-pattern: while(!dut->ready_o) without eval
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Setting valid_i=1 and immediately checking ready_o in a while loop that starts with NO eval() will skip the first clock edge entirely if ready_o is already 1. Use do-while to guarantee at least one edge:
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```cpp
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dut->valid_i = 1;
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do {
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posedge(dut);
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} while (!dut->ready_o);
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```
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