FallenSigh
8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
2 lines
634 B
Makefile
2 lines
634 B
Makefile
obj_dir/Vmod_add_sync.cpp obj_dir/Vmod_add_sync.h obj_dir/Vmod_add_sync.mk obj_dir/Vmod_add_sync__Syms.h obj_dir/Vmod_add_sync__Syms__Slow.cpp obj_dir/Vmod_add_sync___024root.h obj_dir/Vmod_add_sync___024root__0.cpp obj_dir/Vmod_add_sync___024root__0__Slow.cpp obj_dir/Vmod_add_sync___024root__Slow.cpp obj_dir/Vmod_add_sync__pch.h obj_dir/Vmod_add_sync__ver.d obj_dir/Vmod_add_sync_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin /usr/share/verilator/include/verilated_std.sv /usr/share/verilator/include/verilated_std_waiver.vlt sync_rtl/common/defines.vh sync_rtl/common/pipeline_reg.v sync_rtl/mod_add/mod_add_sync.v
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