FallenSigh
8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
10 lines
530 B
Makefile
10 lines
530 B
Makefile
Vmod_add_sync__ALL.o: Vmod_add_sync__ALL.cpp Vmod_add_sync.cpp \
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Vmod_add_sync__pch.h /usr/share/verilator/include/verilated.h \
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/usr/share/verilator/include/verilated_config.h \
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/usr/share/verilator/include/verilatedos.h \
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/usr/share/verilator/include/verilated_types.h \
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/usr/share/verilator/include/verilated_funcs.h Vmod_add_sync__Syms.h \
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Vmod_add_sync.h Vmod_add_sync___024root.h Vmod_add_sync___024root__0.cpp \
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Vmod_add_sync___024root__Slow.cpp Vmod_add_sync___024root__0__Slow.cpp \
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Vmod_add_sync__Syms__Slow.cpp
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