FallenSigh
940946f30c
K-PKE.Decrypt steps 2-3 (FIPS 203 Alg 15), both by reusing Encaps machines: - ST_DEC_SDEC reuses the Encaps TDEC (byteDecode12) machine: only the byte source changes (td_byte mux -> dkp_rd_data; dkp_rd_addr driven by td_ekaddr in SDEC). Decodes dk_pke -> s_hat[j] into bank_a slot j*K, the same layout t_hat uses, so the D3 MAC can read s_hat[j] with the existing addressing. - ST_DEC_NTT reuses the forward-NTT machine (n_slot_max=k_r) to transform u'[i] in place in bank_se rel slots 0..K-1 -> u_hat[i]. Added ST_DEC_NTT to the bank_se read/write muxes and the NTT load/process/arm blocks alongside ST_N/ST_ENC_N. - FSM: DECOMP -> SDEC -> NTT -> DONE. TB verify_d2 checks s_hat[i] (bank_a slot i*K) and u_hat[i] (bank_se rel i) against golden. verify_d1 narrowed to v' only: D2's in-place NTT overwrites u' in bank_se, so u' correctness is now proven transitively via u_hat==NTT(u'). Verified: dec D2 K=2/3/4 all cases PASS; KeyGen + Encaps unregressed.
244 lines
11 KiB
Verilog
244 lines
11 KiB
Verilog
// tb_mlkem_dec_katK_xsim.v - ML-KEM Decaps vs NIST KAT, parametric K (KP) + CASE.
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// D0 stage: stream dk (=sk) into the design via dk_in_* (routed to
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// dk_pke/ek_pke/h/z by region) and ct via c_in_*, pulse start with op=2, and
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// verify the dk PARSE: H(ek) (dbg_dech_o), z (dbg_decz_o), and round-trip a few
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// ek_pke bytes (dbg_byte sel=0) and dk_pke bytes (sel=1) back out of BRAM.
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//
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// xelab -generic_top KP=2|3|4 ; xsim -testplusarg CASE=n
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// dk/ct/ss vectors: sync_rtl/top/TB/vectors/dec_k{K}_c{N}_{dk,ct,ss,ctn,ssn}.hex
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`timescale 1ns/1ps
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module tb_mlkem_dec_katK_xsim;
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parameter KP = 2;
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localparam DKB = 768*KP + 96; // dk (=sk) bytes: 1632/2400/3168
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localparam EKB = 384*KP + 32; // ek_pke bytes within dk
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localparam DKPB = 384*KP; // dk_pke bytes
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localparam CTB = (KP==4) ? 1568 : (32*(10*KP+4)); // ct bytes: 768/1088/1568
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reg clk=0, rst_n=0, start_i=0;
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reg [2:0] k_i;
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reg [255:0] d_i=0, z_i=0, m_i=0;
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wire busy_o, done_o;
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// ek preload port (unused in Decaps; ek_pke comes from dk)
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reg ek_in_we=0; reg [10:0] ek_in_addr=0; reg [7:0] ek_in_byte=0;
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// dk / c input ports
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reg dk_in_we=0; reg [11:0] dk_in_addr=0; reg [7:0] dk_in_byte=0;
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reg c_in_we=0; reg [10:0] c_in_addr=0; reg [7:0] c_in_byte=0;
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wire [255:0] ss_o;
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reg [10:0] dbg_ct_idx_i=0; wire [7:0] dbg_ct_o;
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reg [5:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
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reg dbg_byte_sel_i=0; reg [10:0] dbg_byte_idx_i=0; wire [7:0] dbg_byte_o;
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reg [11:0] dbg_dk_idx_i=0; wire [7:0] dbg_dk_o;
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wire [255:0] dbg_rho_o, dbg_sigma_o, dbg_r_o, dbg_hek_o;
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wire [255:0] dbg_mprime_o, dbg_kbar_o, dbg_decz_o, dbg_dech_o;
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mlkem_top dut (
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.clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(2'd2),
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.d_i(d_i), .z_i(z_i), .msg_i(m_i), .start_i(start_i),
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.busy_o(busy_o), .done_o(done_o),
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.ek_in_we(ek_in_we), .ek_in_addr(ek_in_addr), .ek_in_byte(ek_in_byte),
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.dk_in_we(dk_in_we), .dk_in_addr(dk_in_addr), .dk_in_byte(dk_in_byte),
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.c_in_we(c_in_we), .c_in_addr(c_in_addr), .c_in_byte(c_in_byte),
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.ss_o(ss_o), .dbg_ct_idx_i(dbg_ct_idx_i), .dbg_ct_o(dbg_ct_o),
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.dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
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.dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
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.dbg_dk_idx_i(dbg_dk_idx_i), .dbg_dk_o(dbg_dk_o),
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.dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o),
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.dbg_r_o(dbg_r_o), .dbg_hek_o(dbg_hek_o),
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.dbg_mprime_o(dbg_mprime_o), .dbg_kbar_o(dbg_kbar_o),
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.dbg_decz_o(dbg_decz_o), .dbg_dech_o(dbg_dech_o)
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);
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always #5 clk = ~clk;
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reg [7:0] dk_b [0:DKB-1];
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reg [7:0] ct_b [0:CTB-1];
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reg [7:0] ss_b [0:31];
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integer c, i, j, errors, casenum;
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reg [8*80-1:0] tag, dkfile, ctfile, ssfile;
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initial begin
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if (!$value$plusargs("CASE=%d", casenum)) casenum = 0;
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$sformat(tag, "k%0d", KP);
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$sformat(dkfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_dk.hex", tag, casenum);
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$sformat(ctfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_ct.hex", tag, casenum);
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$sformat(ssfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_ss.hex", tag, casenum);
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$readmemh(dkfile, dk_b);
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$readmemh(ctfile, ct_b);
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$readmemh(ssfile, ss_b);
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k_i = KP[2:0];
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$display("=== ML-KEM K=%0d Decaps KAT case %0d (D0: load+parse) ===", KP, casenum);
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rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
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// ---- stream dk into the design (1 byte/cycle) ----
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for (i = 0; i < DKB; i = i + 1) begin
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dk_in_we = 1'b1; dk_in_addr = i[11:0]; dk_in_byte = dk_b[i];
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@(posedge clk);
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end
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dk_in_we = 1'b0;
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// ---- stream ct into c_in_bram (1 byte/cycle) ----
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for (i = 0; i < CTB; i = i + 1) begin
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c_in_we = 1'b1; c_in_addr = i[10:0]; c_in_byte = ct_b[i];
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@(posedge clk);
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end
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c_in_we = 1'b0; @(posedge clk);
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// ---- run Decaps ----
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start_i=1; @(posedge clk); start_i=0;
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c=0; while(!done_o && c<2000000) begin @(posedge clk); c=c+1; end
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if(!done_o) begin $display("FAIL K=%0d case %0d: timeout", KP, casenum); $finish; end
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$display("=== Decaps D2 done in %0d cyc ===", c);
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verify_d0;
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verify_d1;
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verify_d2;
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if (errors == 0) $display("K=%0d CASE %0d PASS (D2): s_hat + u_hat=NTT(u') OK", KP, casenum);
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else $display("K=%0d CASE %0d FAIL (D2): %0d total errors", KP, casenum, errors);
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$finish;
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end
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initial begin #120000000; $display("FAIL: global timeout"); $finish; end
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// read one stored coefficient at (slot, idx): present addr, wait for the
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// bank read (sd_bram, 1 cyc) + dbg_coeff_r register (1 cyc) + settle.
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task rdcoeff;
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input [5:0] slot; input [7:0] idx; output [11:0] val;
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begin
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dbg_slot_i = slot; dbg_idx_i = idx;
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@(posedge clk); @(posedge clk); @(posedge clk);
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val = dbg_coeff_o;
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end
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endtask
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// D0: verify dk parse. H(ek)=dk[768K+32:+32], z=dk[768K+64:+32] captured into
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// hek_r/z_r (dbg_dech_o/dbg_decz_o). ek_pke=dk[384K:768K+32] in ek_bram
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// (dbg_byte sel=0), dk_pke=dk[0:384K] in dkp_bram (sel=1).
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task verify_d0;
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integer be;
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reg [7:0] got;
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begin
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errors = 0;
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// H(ek)
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for (j = 0; j < 32; j = j + 1)
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if (dbg_dech_o[8*j +: 8] !== dk_b[DKPB + EKB + j]) errors = errors + 1;
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if (errors == 0) $display(" PASS: H(ek) parsed == dk[768K+32 ..]");
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else $display(" FAIL: H(ek) %0d byte mismatches", errors);
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// z
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be = 0;
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for (j = 0; j < 32; j = j + 1)
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if (dbg_decz_o[8*j +: 8] !== dk_b[DKPB + EKB + 32 + j]) be = be + 1;
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if (be == 0) $display(" PASS: z parsed == dk[768K+64 ..]");
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else $display(" FAIL: z %0d byte mismatches", be);
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errors = errors + be;
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// ek_pke round-trip (every 97th byte to keep it quick)
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be = 0;
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for (i = 0; i < EKB; i = i + 97) begin
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dbg_byte_sel_i = 1'b0; dbg_byte_idx_i = i[10:0];
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@(posedge clk); @(posedge clk);
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if (dbg_byte_o !== dk_b[DKPB + i]) begin
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if (be < 6) $display(" ekpke[%0d] got=%02x exp=%02x", i, dbg_byte_o, dk_b[DKPB+i]);
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be = be + 1;
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end
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end
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if (be == 0) $display(" PASS: ek_pke round-trip (BRAM) == dk[384K ..]");
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else $display(" FAIL: ek_pke %0d byte mismatches", be);
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errors = errors + be;
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// dk_pke round-trip
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be = 0;
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for (i = 0; i < DKPB; i = i + 97) begin
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dbg_byte_sel_i = 1'b1; dbg_byte_idx_i = i[10:0];
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@(posedge clk); @(posedge clk);
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if (dbg_byte_o !== dk_b[i]) begin
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if (be < 6) $display(" dkpke[%0d] got=%02x exp=%02x", i, dbg_byte_o, dk_b[i]);
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be = be + 1;
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end
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end
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if (be == 0) $display(" PASS: dk_pke round-trip (BRAM) == dk[0 ..]");
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else $display(" FAIL: dk_pke %0d byte mismatches", be);
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errors = errors + be;
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if (errors == 0) $display(" D0 subcheck PASS: dk parse OK");
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else $display(" D0 subcheck FAIL: %0d errors", errors);
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end
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endtask
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// D1: verify u'[i] (bank_se rel i, abs slot K*K+i) and v' (bank_t rel
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// DEC_VSLOT=2, abs slot K*K+2*K+2) against the decode-decompress golden.
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reg [11:0] up_g [0:255];
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reg [11:0] vp_g [0:255];
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task verify_d1;
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integer i, j, be, ndiff;
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reg [8*100-1:0] fn;
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reg [11:0] got;
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begin
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ndiff = 0;
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// u'[i] is NOT checked here: D2's forward NTT transforms u' in place
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// in bank_se rel 0..K-1, so by the time the run finishes those slots
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// hold u_hat. u' correctness is proven transitively in verify_d2
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// (u_hat == NTT(u') golden). Only v' (bank_t, untouched) is checked.
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// v'
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$sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_vp.hex", KP, casenum);
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$readmemh(fn, vp_g);
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be = 0;
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for (j = 0; j < 256; j = j + 1) begin
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rdcoeff(KP*KP + 2*KP + 2, j[7:0], got);
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if (got !== vp_g[j]) begin
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if (be < 4) $display(" v'[%0d] got=%03x exp=%03x", j, got, vp_g[j]);
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be = be + 1;
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end
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end
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if (be == 0) $display(" PASS: v' == golden (256 coeffs)");
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else $display(" FAIL: v' %0d coeff mismatches", be);
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ndiff = ndiff + be;
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errors = errors + ndiff;
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end
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endtask
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// D2: verify s_hat[i] (bank_a slot i*K, byteDecode12 dk_pke) and
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// u_hat[i] (bank_se rel slot i, = NTT(u'[i])) against golden.
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reg [11:0] sh_g [0:255];
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reg [11:0] uh_g [0:255];
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task verify_d2;
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integer i, j, be, ndiff;
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reg [8*100-1:0] fn;
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reg [11:0] got;
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begin
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ndiff = 0;
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for (i = 0; i < KP; i = i + 1) begin
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// s_hat[i] at bank_a slot i*KP
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$sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_shat_%0d.hex", KP, casenum, i);
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$readmemh(fn, sh_g);
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be = 0;
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for (j = 0; j < 256; j = j + 1) begin
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rdcoeff(i*KP, j[7:0], got);
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if (got !== sh_g[j]) begin
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if (be < 4) $display(" s_hat[%0d][%0d] got=%03x exp=%03x", i, j, got, sh_g[j]);
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be = be + 1;
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end
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end
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if (be == 0) $display(" PASS: s_hat[%0d] == golden", i);
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else $display(" FAIL: s_hat[%0d] %0d mismatches", i, be);
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ndiff = ndiff + be;
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// u_hat[i] at bank_se rel slot i (abs KP*KP + i)
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$sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_uhat_%0d.hex", KP, casenum, i);
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$readmemh(fn, uh_g);
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be = 0;
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for (j = 0; j < 256; j = j + 1) begin
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rdcoeff(KP*KP + i, j[7:0], got);
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if (got !== uh_g[j]) begin
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if (be < 4) $display(" u_hat[%0d][%0d] got=%03x exp=%03x", i, j, got, uh_g[j]);
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be = be + 1;
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end
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end
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if (be == 0) $display(" PASS: u_hat[%0d] == golden", i);
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else $display(" FAIL: u_hat[%0d] %0d mismatches", i, be);
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ndiff = ndiff + be;
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end
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errors = errors + ndiff;
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end
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endtask
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endmodule
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