FallenSigh
8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
31 lines
896 B
HTML
31 lines
896 B
HTML
<!DOCTYPE html>
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<html>
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<head>
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<title>ML-KEM Test Report</title>
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<style>
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body { font-family: monospace; background: #1e1e1e; color: #d4d4d4;
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padding: 20px; }
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h1 { color: #4CAF50; }
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table { border-collapse: collapse; width: 100%; }
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th, td { border: 1px solid #444; padding: 8px; text-align: left; }
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th { background: #333; }
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</style>
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</head>
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<body>
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<h1>ALL TESTS PASSED</h1>
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<p>Generated: 20260624_193336<br>
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Total: 0 vectors (0 pass, 0 fail)<br>
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Elapsed: 0.65s</p>
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<table>
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<tr><th>Module</th><th>Status</th><th>Pass</th><th>Fail</th><th>Time</th></tr>
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<tr>
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<td>mod_add</td>
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<td style="color:#F44336">COMPILE_ERROR</td>
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<td>0</td>
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<td>0</td>
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<td>0.65s</td>
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</tr>
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</table>
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</body>
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</html> |