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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
58 lines
1.6 KiB
C++
58 lines
1.6 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Design internal header
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// See Vmod_add_sync.h for the primary calling header
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#ifndef VERILATED_VMOD_ADD_SYNC___024ROOT_H_
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#define VERILATED_VMOD_ADD_SYNC___024ROOT_H_ // guard
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#include "verilated.h"
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class Vmod_add_sync__Syms;
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class alignas(VL_CACHE_LINE_BYTES) Vmod_add_sync___024root final {
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public:
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// DESIGN SPECIFIC STATE
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VL_IN8(clk,0,0);
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VL_IN8(rst_n,0,0);
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VL_IN8(valid_i,0,0);
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VL_OUT8(ready_o,0,0);
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VL_OUT8(valid_o,0,0);
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VL_IN8(ready_i,0,0);
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CData/*0:0*/ mod_add_sync__DOT__u_pipe__DOT__valid_r;
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CData/*0:0*/ __VstlFirstIteration;
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CData/*0:0*/ __VstlPhaseResult;
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CData/*0:0*/ __VicoFirstIteration;
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CData/*0:0*/ __VicoPhaseResult;
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CData/*0:0*/ __Vtrigprevexpr___TOP__clk__0;
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CData/*0:0*/ __Vtrigprevexpr___TOP__rst_n__0;
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CData/*0:0*/ __VactPhaseResult;
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CData/*0:0*/ __VnbaPhaseResult;
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VL_IN16(a,11,0);
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VL_IN16(b,11,0);
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VL_OUT16(sum,11,0);
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SData/*12:0*/ mod_add_sync__DOT__add_raw;
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SData/*11:0*/ mod_add_sync__DOT__u_pipe__DOT__data_r;
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IData/*31:0*/ __VactIterCount;
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VlUnpacked<QData/*63:0*/, 1> __VstlTriggered;
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VlUnpacked<QData/*63:0*/, 1> __VicoTriggered;
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VlUnpacked<QData/*63:0*/, 1> __VactTriggered;
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VlUnpacked<QData/*63:0*/, 1> __VnbaTriggered;
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// INTERNAL VARIABLES
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Vmod_add_sync__Syms* vlSymsp;
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const char* vlNamep;
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// CONSTRUCTORS
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Vmod_add_sync___024root(Vmod_add_sync__Syms* symsp, const char* namep);
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~Vmod_add_sync___024root();
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VL_UNCOPYABLE(Vmod_add_sync___024root);
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// INTERNAL METHODS
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void __Vconfigure(bool first);
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};
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#endif // guard
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