- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
52 lines
717 B
Markdown
52 lines
717 B
Markdown
# Logging Guidelines
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> How logging is done in this project.
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---
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## Overview
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<!--
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Document your project's logging conventions here.
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Questions to answer:
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- What logging library do you use?
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- What are the log levels and when to use each?
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- What should be logged?
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- What should NOT be logged (PII, secrets)?
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-->
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(To be filled by the team)
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---
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## Log Levels
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<!-- When to use each level: debug, info, warn, error -->
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(To be filled by the team)
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---
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## Structured Logging
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<!-- Log format, required fields -->
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(To be filled by the team)
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---
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## What to Log
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<!-- Important events to log -->
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(To be filled by the team)
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---
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## What NOT to Log
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<!-- Sensitive data, PII, secrets -->
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(To be filled by the team)
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