FallenSigh
5941fee980
Phase 1 complete — all 4 leaf modules verified: - rng_sync.v: 256-bit Galois LFSR PRNG (10/10 PASS) - sample_cbd_sync.v: CBD sampler with keccak_core PRF (2560/2560 PASS) - sample_ntt_sync.v: SHAKE-128 rejection sampling for A matrix (1536/1536 PASS) - xsim Verilog TBs for sha3 module (tb_sha3_xsim.v, tb_sha3_xsim_simple.v, tb_keccak_core_xsim.v)
233 lines
8.2 KiB
Verilog
233 lines
8.2 KiB
Verilog
// tb_sha3_xsim.v - Standard Verilog testbench for sha3_top targeting Vivado xsim
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//
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// Reads test vectors from a hex file using $readmemh.
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// Each line is a single hex number encoding both mode and data:
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// - Upper 8 bits [519:512]: mode[1:0] in bits [513:512]
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// - Lower 512 bits [511:0]: data_i
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// - Total: 130 hex chars per line, NO spaces
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//
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// Drives sha3_top, waits for valid_o, and writes "RESULT: MODE HASH_HEX"
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// to the output file using $fwrite.
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//
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// Parameters:
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// VECTOR_FILE - path to input hex file (default: "vectors/g_basic_input.hex")
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// RESULT_FILE - path to output file (default: "vectors/g_basic_result.hex")
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//
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// Usage:
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// xvlog -sv sha3_top.v tb_sha3_xsim.v
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// xelab tb_sha3_xsim -s tb_sha3_xsim
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// xsim tb_sha3_xsim -R
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`timescale 1ns / 1ps
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module tb_sha3_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/sha3/TB/vectors/g_basic_input.hex";
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parameter RESULT_FILE = "sync_rtl/sha3/TB/vectors/g_basic_result.hex";
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parameter MAX_VECTORS = 256;
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parameter TIMEOUT_CYCLES = 1000;
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [1:0] mode;
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reg [511:0] data_i;
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reg valid_i;
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wire ready_o;
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wire [511:0] hash_o;
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wire valid_o;
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reg ready_i;
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// ================================================================
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// DUT instantiation
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// ================================================================
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sha3_top u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.mode (mode),
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.data_i (data_i),
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.valid_i (valid_i),
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.ready_o (ready_o),
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.hash_o (hash_o),
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.valid_o (valid_o),
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.ready_i (ready_i)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// 520 bits per word: bits[519:512]=padding+mode, bits[511:0]=data_i
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// ================================================================
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reg [519:0] vector_mem [0:MAX_VECTORS-1];
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer result_fd;
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// Test result tracking
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integer pass_count;
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integer fail_count;
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// ================================================================
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// Hex-to-ASCII conversion helper
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// ================================================================
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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if (nibble < 4'd10)
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nibble_to_ascii = 8'h30 + {4'd0, nibble}; // '0'-'9'
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else
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nibble_to_ascii = 8'h41 + ({4'd0, nibble} - 4'd10); // 'A'-'F'
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end
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endfunction
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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// Count loaded vectors
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vec_count = 0;
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// Load vectors from hex file
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$readmemh(VECTOR_FILE, vector_mem);
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// Count non-zero entries to determine actual vector count
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// (XSim leaves unloaded entries as 520'hX)
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (vector_mem[idx] === 520'hx || vector_mem[idx] === 520'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists and is in the correct format.");
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$display(" Each line: <130 hex chars> = {8-bit mode_header, 512-bit data}");
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Open result file
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result_fd = $fopen(RESULT_FILE, "w");
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if (result_fd == 0) begin
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$display("ERROR: Cannot open result file: %s", RESULT_FILE);
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$finish;
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end
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// Initialize DUT inputs
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mode <= 2'd0;
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data_i <= 512'd0;
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valid_i <= 1'b0;
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ready_i <= 1'b1; // always ready to accept output
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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// Extract mode and data from memory word
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// mode in bits [513:512], data in bits [511:0]
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begin
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reg [1:0] vec_mode;
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reg [511:0] vec_data;
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reg [511:0] captured_hash;
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vec_mode = vector_mem[idx][513:512];
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vec_data = vector_mem[idx][511:0];
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$display("INFO: Vector %0d - mode=%0d", idx, vec_mode);
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// Drive DUT
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mode <= vec_mode;
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data_i <= vec_data;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for ready_o (DUT enters PERMUTE state on this cycle)
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// Then wait for valid_o asserted
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cycle_count = 0;
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while (!valid_o && cycle_count < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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end
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if (cycle_count >= TIMEOUT_CYCLES) begin
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$display("ERROR: Timeout waiting for valid_o on vector %0d", idx);
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fail_count = fail_count + 1;
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end else begin
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// Capture hash output
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captured_hash = hash_o;
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pass_count = pass_count + 1;
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// Write result to output file
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// Format: "RESULT: MODE HASH_HEX"
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$fwrite(result_fd, "RESULT: %0d ", vec_mode);
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// Write hash as hex (128 chars for 512 bits)
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begin
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integer bit_idx;
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reg [3:0] nib;
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for (bit_idx = 127; bit_idx >= 0; bit_idx = bit_idx - 1) begin
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nib = captured_hash[(bit_idx*4)+:4];
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$fwrite(result_fd, "%c", nibble_to_ascii(nib));
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end
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end
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$fwrite(result_fd, "\n");
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end
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// One extra cycle for valid_o handshake
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@(posedge clk);
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end // inner begin block for variable scope
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end
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// ============================================================
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// Summary
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// ============================================================
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$fclose(result_fd);
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$display("========================================");
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$display("TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display(" Results written to: %s", RESULT_FILE);
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$display("========================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog
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// ================================================================
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initial begin
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#(TIMEOUT_CYCLES * 10 * 100); // TIMEOUT_CYCLES * 10ns per cycle * extra margin
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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