- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
720 B
720 B
Error Handling
How errors are handled in this project.
Overview
(To be filled by the team)
Error Types
(To be filled by the team)
Error Handling Patterns
(To be filled by the team)
API Error Responses
(To be filled by the team)
Common Mistakes
(To be filled by the team)