Files
mlkem-sync/sync_rtl/sha3_chain/TB/tb_sha3_chain.cpp
FallenSigh ae5f0ca048 feat(sha3_chain): add simple SHA3_G integration test
Phase 3.2: Verifies module chaining works.
- sha3_chain_top.v: 3-state FSM (IDLE→BUSY→DONE), feeds d_in→sha3_top(G)
- Captures rho[255:0] and sigma[511:256] from SHA3-512 output
- Verified: 3/3 bit-exact vs Python G(d||k=2) reference

KG full-path FSM (~11 module chain) deferred — too complex for single dispatch.
2026-06-25 00:22:08 +08:00

180 lines
4.7 KiB
C++

// tb_sha3_chain.cpp - Verilator C++ testbench for sha3_chain_top
//
// Reads test vectors from +VECTOR_FILE= plusarg.
// Format: one 64-char hex string per line (256-bit d).
//
// Drives d_in, asserts start_i, waits for done_o,
// prints "RESULT: RHO_HEX SIGMA_HEX\n" to stdout.
//
// Clock: 10ns period. Reset: 2 cycles.
#include <iostream>
#include <fstream>
#include <string>
#include <cstdlib>
#include <cstdint>
#include "Vsha3_chain_top.h"
#include "verilated.h"
#define CLK_PERIOD_NS 10.0
#define TIMEOUT_CYCLES 500000
static vluint64_t main_time = 0;
double sc_time_stamp() {
return main_time;
}
// One full clock cycle (both edges + eval)
static void posedge(Vsha3_chain_top* dut) {
dut->clk = !dut->clk;
main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
dut->eval();
dut->clk = !dut->clk;
main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
dut->eval();
}
static int hex_char_to_nibble(char c) {
if (c >= '0' && c <= '9') return c - '0';
if (c >= 'A' && c <= 'F') return c - 'A' + 10;
if (c >= 'a' && c <= 'f') return c - 'a' + 10;
return 0;
}
// Parse 64-char hex string into 8 x 32-bit WData words (256 bits).
// Hex is MSB-first (leftmost = bits [255:252]).
// data[0] = bits[31:0], data[7] = bits[255:224].
static void hex_to_256(const std::string& hex, uint32_t data_words[8]) {
for (int w = 0; w < 8; w++) data_words[w] = 0;
int nibble_idx = 0;
for (int i = (int)hex.length() - 1; i >= 0; i--) {
char c = hex[i];
if (c == ' ' || c == '\t') continue;
int nib = hex_char_to_nibble(c);
int word_idx = nibble_idx / 8;
int shift = (nibble_idx % 8) * 4;
if (word_idx < 8) {
data_words[word_idx] |= ((uint32_t)nib << shift);
}
nibble_idx++;
}
}
// Print rho_out and sigma_out as hex (MSB-first), space-separated.
// rho[0]=bits[31:0], rho[7]=bits[255:224]
// sigma[0]=bits[31:0], sigma[7]=bits[255:224]
static void print_256_hex(uint32_t data_words[8]) {
for (int w = 7; w >= 0; w--) {
uint32_t val = data_words[w];
for (int j = 28; j >= 0; j -= 4) {
printf("%01X", (int)((val >> j) & 0xF));
}
}
}
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
// Parse +VECTOR_FILE= plusarg
const char* vector_file = NULL;
for (int i = 1; i < argc; i++) {
std::string arg(argv[i]);
if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
vector_file = argv[i] + 13;
}
}
if (!vector_file) {
std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
return 1;
}
std::ifstream infile(vector_file);
if (!infile.is_open()) {
std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
return 1;
}
// Instantiate DUT
Vsha3_chain_top* dut = new Vsha3_chain_top;
// Initialize
dut->clk = 0;
dut->rst_n = 0;
for (int w = 0; w < 8; w++) dut->d_in[w] = 0;
dut->start_i = 0;
// Reset: 2 full cycles
for (int i = 0; i < 2; i++) posedge(dut);
dut->rst_n = 1;
std::string line;
vluint64_t cycle = 0;
int vec_count = 0;
while (std::getline(infile, line)) {
if (line.empty() || line[0] == '#') continue;
std::string d_hex = line;
// Trim trailing whitespace
while (!d_hex.empty() && (d_hex.back() == ' ' || d_hex.back() == '\t' || d_hex.back() == '\r'))
d_hex.pop_back();
// Parse d
uint32_t d_words[8];
hex_to_256(d_hex, d_words);
for (int w = 0; w < 8; w++) dut->d_in[w] = d_words[w];
// Assert start_i
dut->start_i = 1;
// One cycle with start_i=1
cycle++;
posedge(dut);
// De-assert start_i
dut->start_i = 0;
// Wait for done_o
while (!dut->done_o) {
posedge(dut);
cycle++;
if (cycle > TIMEOUT_CYCLES) {
std::cerr << "ERROR: Timeout waiting for done_o (vec " << vec_count << ")" << std::endl;
goto done;
}
}
// Read outputs
uint32_t rho_words[8], sigma_words[8];
for (int w = 0; w < 8; w++) {
rho_words[w] = dut->rho_out[w];
sigma_words[w] = dut->sigma_out[w];
}
printf("RESULT: ");
print_256_hex(rho_words);
printf(" ");
print_256_hex(sigma_words);
printf("\n");
// One cycle with done_o high, then start_i must be low to return to IDLE
posedge(dut);
cycle++;
vec_count++;
}
done:
infile.close();
delete dut;
if (vec_count == 0) {
std::cerr << "ERROR: No vectors processed" << std::endl;
return 1;
}
return 0;
}