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FallenSigh 52c625b3ef docs(spec): add XSIM testbench conventions to RTL spec

Document Vivado XSIM Verilog testbench conventions:
- File naming, directory structure, TB template
- Clock/reset patterns, valid/ready protocol
- Vector format for
- xsim_run.tcl conventions with -include_dirs requirement
- gen_vectors.py conventions (stdlib only, bit ordering)
- Common mistakes checklist

2026-06-25 20:48:44 +08:00

.claude

feat: init mlkem project with Verilator test framework

2026-06-24 19:43:29 +08:00

.opencode

feat: init mlkem project with Verilator test framework

2026-06-24 19:43:29 +08:00

.trellis

docs(spec): add XSIM testbench conventions to RTL spec

2026-06-25 20:48:44 +08:00

sync_rtl

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules