FallenSigh
d4c3fc86fc
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
313 lines
12 KiB
Verilog
313 lines
12 KiB
Verilog
// tb_poly_mul_xsim.v - Standard Verilog testbench for poly_mul_sync targeting Vivado xsim
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//
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// Reads test vectors from a hex file using $readmemh.
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// Each line is a single hex number encoding 512 coefficient values:
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// - bits [6143:3072]: 256 x 12-bit polynomial A coefficients
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// - bits [3071:0]: 256 x 12-bit polynomial B coefficients
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// - Total: 1536 hex chars per line, NO spaces
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//
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// Drives poly_mul_sync, streams in 256 A+B coefficient pairs via valid/ready,
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// waits for valid_o output, streams out 256 result coefficients,
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// and writes "RESULT: INDEX COEFF_HEX" to the output file.
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//
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// poly_mul_sync FSM: IDLE → LOAD → COMP_CALC → COMP_C0 → COMP_C1 → ... → DONE → IDLE
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// valid_o is asserted during COMP_C0 and COMP_C1 states.
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//
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// Parameters:
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// VECTOR_FILE - path to input hex file (default: "vectors/poly_mul_input.hex")
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// RESULT_FILE - path to output file (default: "vectors/poly_mul_result.hex")
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//
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// Usage:
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// xvlog -sv barrett_mul.v basecase_mul.v poly_mul_zeta_rom.v poly_mul_sync.v tb_poly_mul_xsim.v
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// xelab tb_poly_mul_xsim -s tb_poly_mul_xsim
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// xsim tb_poly_mul_xsim -R
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`timescale 1ns / 1ps
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module tb_poly_mul_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/poly_mul/TB/vectors/poly_mul_input.hex";
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parameter RESULT_FILE = "sync_rtl/poly_mul/TB/vectors/poly_mul_result.hex";
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parameter MAX_VECTORS = 64;
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parameter N_COEFFS = 256;
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parameter TIMEOUT_CYCLES= 100000;
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [11:0] coeff_a_in;
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reg [11:0] coeff_b_in;
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reg valid_i;
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wire ready_o;
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wire [11:0] coeff_out;
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wire valid_o;
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reg ready_i;
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// ================================================================
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// DUT instantiation
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// ================================================================
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poly_mul_sync u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.coeff_a_in (coeff_a_in),
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.coeff_b_in (coeff_b_in),
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.valid_i (valid_i),
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.ready_o (ready_o),
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.coeff_out (coeff_out),
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.valid_o (valid_o),
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.ready_i (ready_i)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// 6144 bits per word:
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// bits [6143:3072]: 256 x 12-bit A coefficients (A[0] at MSB)
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// bits [3071:0]: 256 x 12-bit B coefficients (B[0] at MSB of lower half)
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// ================================================================
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reg [6143:0] vector_mem [0:MAX_VECTORS-1];
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integer vec_count;
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integer idx;
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integer ci;
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integer cycle_count;
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integer result_fd;
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// Test result tracking
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integer pass_count;
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integer fail_count;
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// Temporary storage for coefficients
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reg [11:0] a_coeffs [0:N_COEFFS-1];
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reg [11:0] b_coeffs [0:N_COEFFS-1];
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reg [11:0] output_coeffs [0:N_COEFFS-1];
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// ================================================================
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// Hex-to-ASCII conversion helper
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// ================================================================
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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if (nibble < 4'd10)
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nibble_to_ascii = 8'h30 + {4'd0, nibble}; // '0'-'9'
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else
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nibble_to_ascii = 8'h41 + ({4'd0, nibble} - 4'd10); // 'A'-'F'
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end
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endfunction
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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// Count loaded vectors
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vec_count = 0;
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// Load vectors from hex file
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$readmemh(VECTOR_FILE, vector_mem);
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// Count entries (XSim leaves unloaded entries as 6144'hX)
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (vector_mem[idx] === 6144'hx ||
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vector_mem[idx] === 6144'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists and format is correct.");
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$display(" Each line: 1536 hex chars (768 hex A + 768 hex B)");
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Open result file
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result_fd = $fopen(RESULT_FILE, "w");
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if (result_fd == 0) begin
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$display("ERROR: Cannot open result file: %s", RESULT_FILE);
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$finish;
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end
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// Initialize DUT inputs
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coeff_a_in <= 12'd0;
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coeff_b_in <= 12'd0;
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valid_i <= 1'b0;
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ready_i <= 1'b1; // always ready to accept output
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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begin
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integer out_idx;
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integer input_ok;
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// Extract A and B coefficients from vector memory
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//
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// Memory layout (A in MSB half, B in LSB half):
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// A[0] → bits [6143:6132]
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// A[1] → bits [6131:6120]
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// ...
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// A[255] → bits [3083:3072]
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// B[0] → bits [3071:3060]
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// B[1] → bits [3059:3048]
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// ...
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// B[255] → bits [11:0]
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//
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// Formula: coeff[i] = vector_mem[(N-1-i)*12+11+offset : (N-1-i)*12+offset]
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// A: offset = N*12 = 3072
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// B: offset = 0
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for (ci = 0; ci < N_COEFFS; ci = ci + 1) begin
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a_coeffs[ci] = vector_mem[idx][(N_COEFFS-1-ci)*12 + 11 + N_COEFFS*12
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: (N_COEFFS-1-ci)*12 + N_COEFFS*12];
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b_coeffs[ci] = vector_mem[idx][(N_COEFFS-1-ci)*12 + 11
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: (N_COEFFS-1-ci)*12];
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end
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$display("INFO: Vector %0d", idx);
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input_ok = 1;
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// ----------------------------------------------------
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// LOAD phase: stream in 256 A+B coefficient pairs
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// ----------------------------------------------------
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for (ci = 0; ci < N_COEFFS && input_ok; ci = ci + 1) begin
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// Wait for ready_o before driving next input
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cycle_count = 0;
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while (!ready_o && cycle_count < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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end
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if (cycle_count >= TIMEOUT_CYCLES) begin
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$display("ERROR: Timeout waiting for ready_o (input ci=%0d) on vector %0d",
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ci, idx);
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fail_count = fail_count + 1;
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input_ok = 0;
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end else begin
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coeff_a_in <= a_coeffs[ci];
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coeff_b_in <= b_coeffs[ci];
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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end
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end
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if (!input_ok) begin
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// Skip output reading for this failed vector
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@(posedge clk);
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end else begin
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// ----------------------------------------------------
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// OUTPUT phase: wait for valid_o and stream out results
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// poly_mul_sync enters COMP_CALC→COMP_C0 state after LOAD.
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// valid_o is asserted during COMP_C0 and COMP_C1.
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// There may be cycles with valid_o=0 between outputs
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// (during COMP_CALC transitions).
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// ----------------------------------------------------
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out_idx = 0;
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while (out_idx < N_COEFFS) begin
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// Wait for valid_o
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cycle_count = 0;
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while (!valid_o && cycle_count < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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end
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if (cycle_count >= TIMEOUT_CYCLES) begin
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$display("ERROR: Timeout waiting for valid_o (output %0d) on vector %0d",
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out_idx, idx);
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fail_count = fail_count + 1;
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out_idx = N_COEFFS; // break out
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end else begin
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// Capture output coefficient
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output_coeffs[out_idx] = coeff_out;
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out_idx = out_idx + 1;
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@(posedge clk); // ready_i=1, consume output
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end
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end
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pass_count = pass_count + 1;
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// Write result to output file
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// Format: "RESULT: INDEX COEFF_HEX"
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$fwrite(result_fd, "RESULT: %0d ", idx);
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// Write all 256 output coeffs as hex (3 chars each = 768 total)
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begin
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integer oi;
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reg [3:0] nib;
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for (oi = 0; oi < N_COEFFS; oi = oi + 1) begin
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nib = output_coeffs[oi][11:8];
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$fwrite(result_fd, "%c", nibble_to_ascii(nib));
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nib = output_coeffs[oi][7:4];
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$fwrite(result_fd, "%c", nibble_to_ascii(nib));
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nib = output_coeffs[oi][3:0];
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$fwrite(result_fd, "%c", nibble_to_ascii(nib));
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end
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end
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$fwrite(result_fd, "\n");
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// Wait for DUT to return to IDLE before next vector
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// The DUT goes to S_DONE then S_IDLE after all outputs
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cycle_count = 0;
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while (!ready_o && cycle_count < 1000) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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end
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end
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// Extra cycle before next vector
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@(posedge clk);
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end // inner begin block
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end
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// ============================================================
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// Summary
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// ============================================================
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$fclose(result_fd);
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$display("========================================");
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$display("TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display(" Results written to: %s", RESULT_FILE);
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$display("========================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog
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// ================================================================
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initial begin
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// TIMEOUT_CYCLES * 10ns per cycle * 10x margin
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#(TIMEOUT_CYCLES * 10 * 10);
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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