FallenSigh
0fa7f48ed4
mlkem_top instantiates sd_bram (ek/dk byte buffers) but create_project.tcl was missing it -- elaboration would fail. Add sync_rtl/storage/sd_bram.v to match xsim_run.tcl exactly. Also clarify the run flow: runtime=all means launch_simulation runs to the TB $finish; a manual 'run all' afterwards trips the 120ms watchdog and prints a spurious timeout. Verified: vivado -mode batch builds the project (0 errors) and the simulation prints 'K=2 CASE 0 PASS: ek==pk, dk==sk'.
125 lines
6.0 KiB
Tcl
125 lines
6.0 KiB
Tcl
# create_project.tcl — 自动创建 Vivado 工程（仿真用），加载 ML-KEM KeyGen
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# 顶层 mlkem_top 及其全部叶子算子与参数化 KAT testbench。
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#
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# 与已验证的 XSIM 流程（sync_rtl/top/TB/xsim_run.tcl）保持一致：
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# - 加载 mlkem_top 实际依赖的全部 RTL 源文件（含 sd_bram 存储）
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# - 顶层仿真模块 = tb_mlkem_kg_katK_xsim
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# - 运行时安全等级由 generic KP（2/3/4）选择，用例号由 +CASE 选择
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#
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# Usage:
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# cd ~/Dev/mlkem
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# vivado -mode batch -source create_project.tcl
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# 或在 Vivado Tcl Console 中：
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# source create_project.tcl
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#
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# 切换被仿真的配置（默认 KP=2, CASE=0）：编辑下方 SIM_KP / SIM_CASE 后重跑，
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# 或在工程打开后执行：
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# set_property generic "KP=4" [get_filesets sim_1]
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# set_property -name {xsim.simulate.xsim.more_options} -value {-testplusarg CASE=2} -objects [get_filesets sim_1]
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set PROJECT_NAME mlkem
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set PROJECT_DIR [file normalize [file dirname [info script]]]
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# 默认仿真配置（可改）
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set SIM_KP 2 ;# ML-KEM 方案：2=512, 3=768, 4=1024
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set SIM_CASE 0 ;# KAT 用例号（K=2: 0..4, K=3/4: 0..2）
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# 仅仿真工程，无需指定 FPGA part（XSim 用默认 part 即可）
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create_project -force ${PROJECT_NAME} ${PROJECT_DIR}/vivado_prj
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set_property target_simulator XSim [current_project]
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# ===================================================================
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# RTL 源文件 —— 与 xsim_run.tcl 完全一致
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# ===================================================================
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# ── SHA3 / Keccak ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_round.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_core.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/sha3_top_shared.v
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# ── 采样（共享 keccak_core 变体）──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_cbd/sample_cbd_sync_shared.v
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# ── NTT ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/barrett_mul.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/zeta_rom.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/butterfly_unit.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/ntt_core.v
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# ── 多项式乘法 ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/basecase_mul.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_zeta_rom.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_sync.v
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# ── 存储（ek/dk 字节缓冲，registered-read BRAM）──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/sd_bram.v
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# ── 顶层 KeyGen 集成 ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v
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# ── 参数化 KAT testbench ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_kg_katK_xsim.v
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# ===================================================================
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# 仿真设置
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# ===================================================================
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# 顶层仿真模块
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set_property top tb_mlkem_kg_katK_xsim [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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# `include "sync_rtl/common/defines.vh" 的包含路径（相对工程根）
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set_property include_dirs ${PROJECT_DIR} [get_filesets sim_1]
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# 运行时安全等级：通过 TB 顶层 generic KP 传入（2/3/4）
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set_property generic "KP=${SIM_KP}" [get_filesets sim_1]
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# 跑到 $finish 为止；显式时标（XSim 默认已加 --relax，勿重复）
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set_property -name {xsim.simulate.runtime} -value {all} -objects [get_filesets sim_1]
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set_property -name {xsim.elaborate.xelab.more_options} \
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-value {--timescale 1ns/1ps} -objects [get_filesets sim_1]
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# ===================================================================
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# 测试向量：Vivado GUI 在 vivado_prj/mlkem.sim/sim_1/behav/xsim/ 下运行
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# xsim，而 TB 的 $readmemh 路径相对工程根（sync_rtl/top/TB/vectors/…）。
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# 用 compile 的 pre-hook（在 xsim 工作目录、且在 compile/elaborate/simulate
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# 之前执行）把整套 KAT 向量复制到同名相对路径下；CASE 经 -testplusarg 选择。
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#
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# 注意：2019.2 的 sim_1 没有 simulate.tcl.pre 属性，且追加 -tclbatch 会排在
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# Vivado 自带（含 "run all"）的 tclbatch 之后、即仿真跑完才执行（太迟）。
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# 因此用 xsim.compile.tcl.pre —— 它最早执行且就在仿真工作目录里。
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# ===================================================================
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set pre_tcl [file join ${PROJECT_DIR} vivado_prj copy_vectors_pre.tcl]
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set fp [open $pre_tcl w]
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puts $fp "# Auto-generated by create_project.tcl: 复制 KAT 向量到 xsim 工作目录"
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puts $fp "file mkdir sync_rtl/top/TB/vectors"
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puts $fp "foreach v \[glob -nocomplain [file join ${PROJECT_DIR} sync_rtl top TB vectors kat_k*_c*_*.hex]\] {"
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puts $fp " file copy -force \$v sync_rtl/top/TB/vectors/"
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puts $fp "}"
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puts $fp "puts {\[create_project\] KAT vectors copied to xsim working dir}"
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close $fp
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set_property -name {xsim.compile.tcl.pre} -value $pre_tcl -objects [get_filesets sim_1]
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set_property -name {xsim.simulate.xsim.more_options} \
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-value "-testplusarg CASE=${SIM_CASE}" \
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-objects [get_filesets sim_1]
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# ===================================================================
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puts "========================================"
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puts " Project created: ${PROJECT_DIR}/vivado_prj/${PROJECT_NAME}.xpr"
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puts " 仿真配置: ML-KEM K=${SIM_KP}, KAT CASE=${SIM_CASE}"
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puts ""
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puts " 运行仿真（runtime=all，会自动跑到 TB 的 \$finish）："
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puts " - GUI: 打开工程后点 Run Simulation，或 Tcl Console: launch_simulation"
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puts " - batch: vivado -mode batch -source create_project.tcl 后，"
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puts " 另开: open_project vivado_prj/mlkem.xpr; launch_simulation"
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puts " （勿在 launch_simulation 后再手动 run all —— 仿真已到 \$finish，"
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puts " 再 run 会触发 TB 的 120ms 看门狗误报 timeout）"
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puts " 期望输出: K=${SIM_KP} CASE ${SIM_CASE} PASS: ek==pk, dk==sk"
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puts ""
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puts " 切换配置（如 K=4）：编辑脚本顶部 SIM_KP/SIM_CASE 重跑本脚本，"
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puts " 或在已打开工程中改 generic 后 relaunch_sim。"
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puts "========================================"
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