FallenSigh
4d3adc6b57
Replace the single async-read polymem[0:28*256-1] with 3 polynomial-indexed banks (bank_a A_hat / bank_se s_hat||e_hat / bank_t t_hat), addressed by abs_slot - base_slot. Still async-read here -- a pure refactor that validates bank sizing and base-relative addressing with zero timing change before stage 2b converts them to registered sd_bram + read-ahead pipelines. 11/11 KAT PASS, byte-exact, 0 file-not-found.
48 lines
2.4 KiB
Markdown
48 lines
2.4 KiB
Markdown
# Phase 2: polymem -> BRAM banks
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## Goal
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Replace the single multi-port async-read `reg [11:0] polymem [0:28*256-1]` with
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registered-read `sd_bram` banks that infer real BRAM (ASIC: compiled SRAM).
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## Bank split (all sd_bram, W=12, 1R+1W registered)
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- bank_a : A_hat[i][j], slots 0..K^2-1 -> D=4096 (KMAX^2*256), A=12
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- bank_se: s_hat[i] then e_hat[i] -> D=2048 (2*KMAX*256), A=11
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relative slot = abs_slot - slot_s_rt (s: 0..K-1, e: K..2K-1)
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- bank_t : t_hat[i], slots slot_t_rt.. -> D=1024 (KMAX*256), A=10
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relative slot = abs_slot - slot_t_rt
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## Port budget (verified disjoint)
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- poly_mul LOAD vs ACCUMULATE never overlap; ST_N/ST_M/ST_E are disjoint
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top-states. => each bank needs only 1R+1W. sd_bram fits.
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- bank_t ST_M-acc reads t_hat[idx] (j>0 source) and writes t_hat[idx] result
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same cycle: 1R+1W, read-old/write-new. Prefetch keeps read AHEAD of write
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(monotonic idx), so no same-pass RAW hazard.
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## Read sites (all need 1-cycle read-ahead vs async today)
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- ntt_in (ST_N load) <- bank_se[n_slot]
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- e_c0,e_c1 (ST_E) <- bank_se (dk) or bank_t (ek); SERIALIZE the
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two reads across the 3-byte/pair window
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- pm_a_in (ST_M load) <- bank_a[m_aslot]
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- pm_b_in (ST_M load) <- bank_se[m_j]
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- m_acc_src (ST_M acc) <- bank_se[K+m_i] (j==0) or bank_t[m_i] (j>0)
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- dbg_coeff_o (not on KAT path) <- route by slot range (compile-only)
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## Write sites
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- ST_A: bank_a[a_slot] <= snt_coeff
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- ST_C: bank_se[c_slot-slot_s] <= cbd_modq
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- ST_N: bank_se[n_slot] <= ntt_coeff (write-back, same slot)
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- ST_M-acc: bank_t[m_i] <= m_accq
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## Read-ahead strategy
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Cores hold ready_o high through entire LOAD (no mid-stream backpressure) =>
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fixed 1-cycle skew. Pattern: advance a read-address pointer 1 cycle ahead of
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the consumer index; delay the consumer's valid by 1 cycle ("prime the pipe").
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For ST_M-acc (irregular pm_vo cadence 0,1,1): 2-entry prefetch skid buffer,
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read pointer runs monotonically ahead of write pointer.
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## Checkpoints (KAT-gated: 11 cases, byte-exact, 0 file-not-found)
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- 2a: split polymem -> 4 ASYNC-read banks (pure refactor, zero timing change).
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Validates bank sizing + base-relative addressing + debug mux. COMMIT.
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- 2b: convert banks to registered sd_bram + add read-ahead pipelines to every
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consumer FSM (ST_N, ST_E, ST_M load, ST_M acc). COMMIT.
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