- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
878 B
878 B
Component Guidelines
How components are built in this project.
Overview
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Component Structure
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Props Conventions
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Styling Patterns
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Accessibility
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Common Mistakes
(To be filled by the team)