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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
46 lines
1.4 KiB
Python
46 lines
1.4 KiB
Python
"""result_checker.py - Compares simulation output against expected values."""
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def check_results(got: list[str], expected_file: str) -> tuple[int, int]:
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"""Compare Verilator output against expected values.
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Args:
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got: List of result strings from simulation (hex values).
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expected_file: Path to file containing expected hex values, one per line.
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Returns:
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tuple[int, int]: (num_pass, num_fail).
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"""
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# Read expected values
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expected = []
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try:
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with open(expected_file, 'r') as f:
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for line in f:
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line = line.strip()
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if line and not line.startswith('#'):
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expected.append(line)
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except FileNotFoundError:
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print(f"[ERROR] Expected file not found: {expected_file}")
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return (0, len(got))
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num_pass = 0
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num_fail = 0
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max_len = max(len(got), len(expected))
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for i in range(max_len):
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got_val = got[i].upper() if i < len(got) else 'MISSING'
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exp_val = expected[i].upper() if i < len(expected) else 'MISSING'
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if got_val == exp_val:
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num_pass += 1
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else:
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num_fail += 1
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if num_fail <= 5: # Only show first 5 failures
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print(f" MISMATCH[{i}]: got={got_val}, expected={exp_val}")
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if num_fail > 5:
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print(f" ... and {num_fail - 5} more mismatches")
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return (num_pass, num_fail)
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