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Document Vivado XSIM Verilog testbench conventions: - File naming, directory structure, TB template - Clock/reset patterns, valid/ready protocol - Vector format for - xsim_run.tcl conventions with -include_dirs requirement - gen_vectors.py conventions (stdlib only, bit ordering) - Common mistakes checklist
15 lines
559 B
Markdown
15 lines
559 B
Markdown
# RTL Specifications
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## Pre-Development Checklist
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Before writing RTL code or testbenches, read:
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1. [Verilator Conventions](./verilator-conventions.md) — for C++ Verilator testbenches
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2. [XSIM Testbench Conventions](./xsim-tb-conventions.md) — for Vivado XSIM Verilog testbenches
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## Files
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| File | Purpose |
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|------|---------|
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| `verilator-conventions.md` | Verilator 5.046 C++ testbench conventions (clock, timing, valid/ready protocol) |
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| `xsim-tb-conventions.md` | Vivado XSIM Verilog testbench conventions (template, vector format, TCL scripts) |
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