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8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
13 lines
329 B
JSON
13 lines
329 B
JSON
{
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"verilator": {
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"path": "verilator",
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"compile_args": ["-Wall", "--cc", "--build", "--timing", "--exe"]
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},
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"clock_period_ns": 10.0,
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"timeout_cycles": 100000,
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"rtl_root": "sync_rtl",
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"vector_root": "test_framework/modules/{module}/vectors",
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"report_root": "test_framework/reports",
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"keep_vectors": false
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}
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