FallenSigh
f211dc3c55
- sync_rtl/kg/TB/tb_kg_xsim.v + xsim_run.tcl - sync_rtl/en/TB/tb_en_xsim.v + xsim_run.tcl - sync_rtl/de/TB/tb_de_xsim.v + xsim_run.tcl Run individual tests: ./run_tb.sh kg (KeyGen only, ~47K cycles) ./run_tb.sh en (Encaps only) ./run_tb.sh de (Decaps only)
239 lines
8.1 KiB
Verilog
239 lines
8.1 KiB
Verilog
// tb_kg_xsim.v - KeyGen-only KAT testbench for mlkem_top
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//
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// Runs full ML-KEM flow (kg→en→de) but only CHECKS KeyGen results.
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// Uses existing vector files from sync_rtl/top/TB/vectors/.
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//
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// Usage:
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// xvlog -sv -i . <all_deps>.v sync_rtl/kg/TB/tb_kg_xsim.v
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// xelab tb_kg_xsim -s tb_kg_xsim --timescale 1ns/1ps
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// xsim tb_kg_xsim -R
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`timescale 1ns / 1ps
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module tb_kg_xsim;
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parameter VECTOR_FILE = "sync_rtl/top/TB/vectors/mlkem_top_input.hex";
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parameter EXPECTED_FILE = "sync_rtl/top/TB/vectors/mlkem_top_expected.hex";
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parameter MAX_VECTORS = 16;
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parameter TIMEOUT_CYCLES = 10000000;
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parameter K_PARAM = 4;
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localparam PK_WIDTH = 12 * K_PARAM * 256;
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localparam SK_WIDTH = 12 * K_PARAM * 256;
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localparam EXP_PK_WIDTH = 6400;
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localparam EXP_SK_WIDTH = 13056;
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localparam EXP_CT_WIDTH = 6144;
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localparam EXP_SS_WIDTH = 256;
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// DUT signals
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reg clk;
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reg rst_n;
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reg [1:0] mode;
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reg [2:0] i_k;
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reg valid_i;
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wire ready_o;
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wire [PK_WIDTH-1:0] pk_o;
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wire [SK_WIDTH-1:0] sk_o;
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wire pk_valid;
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wire sk_valid;
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wire [EXP_CT_WIDTH*K_PARAM/2-1:0] ct_o;
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wire [255:0] K_o;
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wire ct_valid;
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wire K_valid;
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wire [255:0] K_o_dec;
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wire K_valid_dec;
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wire done_o;
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// DUT instantiation
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mlkem_top #(.K(K_PARAM)) u_dut (
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.clk(clk), .rst_n(rst_n), .mode(mode), .i_k(i_k),
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.valid_i(valid_i), .ready_o(ready_o),
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.pk_o(pk_o), .sk_o(sk_o), .pk_valid(pk_valid), .sk_valid(sk_valid),
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.ct_o(ct_o), .K_o(K_o), .ct_valid(ct_valid), .K_valid(K_valid),
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.K_o_dec(K_o_dec), .K_valid_dec(K_valid_dec), .done_o(done_o)
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);
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initial clk = 1'b0;
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always #5 clk = ~clk;
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reg [767:0] input_mem [0:MAX_VECTORS-1];
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reg [25855:0] expected_mem [0:MAX_VECTORS-1];
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integer vec_count, idx, kg_pass, kg_fail;
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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nibble_to_ascii = (nibble < 4'd10) ? (8'h30 + {4'd0, nibble}) : (8'h41 + ({4'd0, nibble} - 4'd10));
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endfunction
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task print_hex256;
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input [255:0] val;
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input [256*8:1] label;
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integer bi;
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begin
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$write("%s: ", label);
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for (bi = 63; bi >= 0; bi = bi - 1)
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$write("%c", nibble_to_ascii(val[(bi*4)+:4]));
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$write("\n");
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end
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endtask
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integer wfd_result;
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task wait_for_done;
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input [256*8:1] op_name;
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integer cyc;
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begin
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cyc = 0;
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while (!done_o && cyc < TIMEOUT_CYCLES) begin @(posedge clk); cyc = cyc + 1; end
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if (cyc >= TIMEOUT_CYCLES) begin
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$display("ERROR: %s timeout after %0d cycles", op_name, TIMEOUT_CYCLES);
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wfd_result = 0;
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end else begin
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$display("INFO: %s done after %0d cycles", op_name, cyc);
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wfd_result = 1;
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end
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end
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endtask
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initial begin
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vec_count = 0;
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$readmemh(VECTOR_FILE, input_mem);
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$readmemh(EXPECTED_FILE, expected_mem);
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begin
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integer found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (input_mem[idx] === 768'hx || input_mem[idx] === 768'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$finish;
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end
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$display("====================================================");
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$display("MLKEM_TOP KeyGen-ONLY KAT TESTBENCH");
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$display(" Vectors loaded: %0d", vec_count);
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$display("====================================================");
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mode <= 2'd0;
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i_k <= 3'd2;
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valid_i <= 1'b0;
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rst_n <= 1'b0;
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repeat (5) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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force u_dut.chain_kc_ready_o = 1'b1;
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force u_dut.ntt_valid_o = 1'b1;
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kg_pass = 0; kg_fail = 0;
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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reg [255:0] d_val, msg_val, z_val;
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reg [EXP_PK_WIDTH-1:0] exp_pk;
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reg [EXP_SK_WIDTH-1:0] exp_sk;
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d_val = input_mem[idx][767:512];
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msg_val = input_mem[idx][511:256];
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z_val = input_mem[idx][255:0];
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exp_sk = expected_mem[idx][EXP_SS_WIDTH + EXP_CT_WIDTH +: EXP_SK_WIDTH];
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exp_pk = expected_mem[idx][EXP_SS_WIDTH + EXP_CT_WIDTH + EXP_SK_WIDTH +: EXP_PK_WIDTH];
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$display("--- Vector %0d: KeyGen ---", idx);
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print_hex256(d_val, " d ");
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// KeyGen
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force u_dut.d_reg = d_val;
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mode <= 2'b00;
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i_k <= 3'd2;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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wait_for_done("KeyGen");
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if (wfd_result) begin
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release u_dut.d_reg;
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if (pk_valid && sk_valid) begin
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if (pk_o[EXP_PK_WIDTH-1:0] == exp_pk) begin
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$display(" PASS: pk matches expected");
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kg_pass = kg_pass + 1;
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end else begin
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$display(" FAIL: pk mismatch");
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kg_fail = kg_fail + 1;
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end
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if (sk_o[SK_WIDTH-1:0] == exp_sk[SK_WIDTH-1:0])
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$display(" PASS: sk matches expected");
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else begin
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$display(" FAIL: sk mismatch");
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kg_fail = kg_fail + 1;
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end
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end else begin
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$display(" FAIL: pk_valid=%b sk_valid=%b", pk_valid, sk_valid);
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kg_fail = kg_fail + 1;
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end
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end else begin
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release u_dut.d_reg;
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$display(" FAIL: KeyGen timeout");
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kg_fail = kg_fail + 1;
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rst_n <= 1'b0; repeat (5) @(posedge clk); rst_n <= 1'b1;
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force u_dut.chain_kc_ready_o = 1'b1; force u_dut.ntt_valid_o = 1'b1;
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@(posedge clk);
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end
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repeat (2) @(posedge clk);
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// Encaps (run but don't check)
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force u_dut.m_reg = msg_val;
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mode <= 2'b01;
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i_k <= 3'd2;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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wait_for_done("Encaps");
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if (wfd_result) release u_dut.m_reg;
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else begin
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release u_dut.m_reg;
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rst_n <= 1'b0; repeat (5) @(posedge clk); rst_n <= 1'b1;
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force u_dut.chain_kc_ready_o = 1'b1; force u_dut.ntt_valid_o = 1'b1;
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@(posedge clk);
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end
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repeat (2) @(posedge clk);
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// Decaps (run but don't check)
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force u_dut.z_reg = z_val;
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mode <= 2'b10;
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i_k <= 3'd2;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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wait_for_done("Decaps");
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if (wfd_result) release u_dut.z_reg;
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else begin
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release u_dut.z_reg;
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rst_n <= 1'b0; repeat (5) @(posedge clk); rst_n <= 1'b1;
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force u_dut.chain_kc_ready_o = 1'b1; force u_dut.ntt_valid_o = 1'b1;
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@(posedge clk);
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end
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repeat (2) @(posedge clk);
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end
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release u_dut.chain_kc_ready_o;
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release u_dut.ntt_valid_o;
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$display("====================================================");
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$display("KEYGEN TEST COMPLETE");
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$display(" PASS: %0d FAIL: %0d", kg_pass, kg_fail);
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$display("====================================================");
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$finish;
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end
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initial begin
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#(TIMEOUT_CYCLES * 10 * 100);
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$display("FATAL: Global simulation timeout");
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$finish;
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end
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endmodule
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