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Document Vivado XSIM Verilog testbench conventions: - File naming, directory structure, TB template - Clock/reset patterns, valid/ready protocol - Vector format for - xsim_run.tcl conventions with -include_dirs requirement - gen_vectors.py conventions (stdlib only, bit ordering) - Common mistakes checklist
559 B
559 B
RTL Specifications
Pre-Development Checklist
Before writing RTL code or testbenches, read:
- Verilator Conventions — for C++ Verilator testbenches
- XSIM Testbench Conventions — for Vivado XSIM Verilog testbenches
Files
| File | Purpose |
|---|---|
verilator-conventions.md |
Verilator 5.046 C++ testbench conventions (clock, timing, valid/ready protocol) |
xsim-tb-conventions.md |
Vivado XSIM Verilog testbench conventions (template, vector format, TCL scripts) |